ICS1893CFILF datasheet(116/127 Pages) RENESAS

116 / 127 page

ICS1893CF, Rev. K, 05/13/10

May, 2010

116

Chapter 9 DC and AC Operating Conditions

ICS1893CF Data Sheet - Release

9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion

Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The

time periods consist of timings of signals on the following pins:

• TP_RX (that is, TP_RXP and TP_RXN)

• CRS

• COL

Figure 9-15 shows the timing diagram for the time periods.

† The IEEE maximum is 20 bit times.

‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.

Figure 9-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram

Table 9-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing

Time

Period

Parameter

Conditions

Min.

Typ. Max.

Units

First Bit of /J/ into TP_RX to CRS Assert †

–

Bit times

First Bit of /J/ into TP_RX while

Transmitting Data to COL Assert †

Half-Duplex Mode

–

Bit times

First Bit of /T/ into TP_RX to CRS

De-Assert ‡

–13

–

Bit times

First Bit of /T/ Received into TP_RX to

COL De-Assert ‡

Half-Duplex Mode

–

Bit times

First bit

First bit of /T/

† Shown

unscrambled.

TP_RX†

CRS

COL

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