MPC850 datasheet(42/72 Pages) FREESCALE

部品番号	MPC850

部品情報	PowerQUICC™ Integrated Communications Processor Hardware Specifications

PDF	72 Pages

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メーカー	FREESCALE [Freescale Semiconductor, Inc]

ホームページ	http://www.freescale.com

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram

8.2

IDMA Controller AC Electrical Specifications

Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42.

Figure 39. IDMA External Requests Timing Diagram

Table 14. IDMA Controller Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

DREQ setup time to clock high

7.00

—

DREQ hold time from clock high

3.00

—

SDACK assertion delay from clock high

—

12.00

SDACK negation delay from clock low

—

12.00

SDACK negation delay from TA low

—

20.00

SDACK negation delay from clock high

—

15.00

TA assertion to falling edge of the clock setup time (applies to external TA)7.00

—

CLKOUT

DATA-IN

DATA-OUT

DREQ

(Input)

CLKOUT

(Output)

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