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MPC850 データシート(PDF) 13 Page - Freescale Semiconductor, Inc |
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MPC850 データシート(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 13 Bus Signal Timing B22 CLKOUT rising edge to CS asserted GPCM ACS = 00 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0,1 — 8.00 — 8.00 — 8.00 — 50.00 ns B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns B24 A[6–31] to CS asserted GPCM ACS = 10, TRLX = 0. 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B24a A[6–31] to CS asserted GPCM ACS = 11, TRLX = 0 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B25 CLKOUT rising edge to OE, WE[0–3] asserted — 9.00 — 9.00 — 9.00 — 50.00 ns B26 CLKOUT rising edge to OE negated 2.00 9.00 2.00 9.00 2.00 9.00 — 50.00 ns B27 A[6–31] to CS asserted GPCM ACS = 10, TRLX = 1 23.00 — 36.00 — 29.00 — 1.250 50.00 ns B27a A[6–31] to CS asserted GPCM ACS = 11, TRLX = 1 28.00 — 43.00 — 36.00 — 1.500 50.00 ns B28 CLKOUT rising edge to WE[0–3] negated GPCM write access CSNT = 0 — 9.00 — 9.00 — 9.00 — 50.00 ns B28a CLKOUT falling edge to WE[0–3] negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 — 12.00 — 14.00 — 13.00 0.250 50.00 ns Table 6. Bus Operation Timing 1 (continued) Num Characteristic 50 MHz 66 MHz 80 MHz FFACT Cap Load (default 50 pF) Unit Min Max Min Max Min Max |
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