JS28F640J3F75 datasheet(33/67 Pages) NUMONYX

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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Datasheet

8.1.2

Output Disable

With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled.

Output signals DQ[15:0] are placed in a high-impedance state.

8.2

Bus Writes

Writing or Programming to the device, is where the host writes information or data into

the flash device for non-volatile storage. When the flash device is programmed, ‘ones’

are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase

operation must be performed. Writing commands to the Command User Interface (CUI)

enables various modes of operation, including the following:

• Reading of array data

• Common Flash Interface (CFI) data

• Identifier codes, inspection, and clearing of the Status Register

• Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH)

Erasing is performed on a block basis – all flash cells within a block are erased together.

Any information or data previously stored in the block will be lost. Erasing is typically

done prior to programming. The Block Erase command requires appropriate command

data and an address within the block to be erased. The Byte/Word Program command

requires the command and address of the location to be written. Set Block Lock-Bit

commands require the command and block within the device to be locked. The Clear

Block Lock-Bits command requires the command and address within the device to be

cleared.

The CUI does not occupy an addressable memory location. It is written when the device

is enabled and WE# is active. The address and data needed to execute a command are

latched on the rising edge of WE# or CEX (CEX low is defined as the combination of pins

CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of

pins CE0, CE1, and CE2 that disable the device. See Table 17 on page 30). Standard

microprocessor write timings are used.

Table 18: Enhanced Configuration Register

Reserved

Page

Length

Reserved

ECR

BITS

DESCRIPTION

NOTES

ECR[15:14]

RFU

All bits should be set to 0.

ECR.13

• “1” = 8-Word Page mode

• “0” = 8-Word Page mode (Default)

Either “1” or “0” is for 8-word sense in page

mode.

ECR[12:0]

RFU

All bits should be set to 0.

Table 19: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition

Command

Bus

Cycles

Required

First Bus Cycle

Second Bus Cycle

Oper

Addr(1)

Data

Oper

Addr(1)

Data

Set Enhanced Configuration

Write

ECD

0060h

Write

ECD

0004h

1. ECD = Enhanced Configuration Register Data

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