AD9992BBCZ datasheet(26/92 Pages) AD

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AD9992

Rev. C | Page 26 of 92

VERTICAL SHIFT

VERT. SHIFT

CCD OUTPUT

SHP

SHD

H1/H3/H5/H7

H2/H4/H6/H8

HBLK

PBLK

CLPOB

OPTICAL BLACK

DUMMY

EFFECTIVE PIXELS

OPTICAL BLACK

NOTES

1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).

Figure 32. Horizontal Sequence Example

VERTICAL TIMING GENERATION

The AD9992 provides a flexible solution for generating vertical

CCD timing and can support multiple CCDs and different

system architectures. The vertical transfer clocks are used to shift

each line of pixels into the horizontal output register of the CCD.

The AD9992 allows these outputs to be individually programmed

into various readout configurations by using a 4-step process.

Figure 33 shows an overview of how the vertical timing is

generated in four steps.

The individual pulse patterns for XV1 to XV24 are created

by using the vertical pattern group registers.

The V-pattern groups are used to build the sequences,

which is when additional information is added.

The readout for an entire field is constructed by dividing

the field into different regions and then assigning a

sequence to each region.

Each field can contain up to nine different regions to

accommodate different steps of the readout, such as high

speed line shifts and unique vertical line transfers. The

total number of V-patterns, V-sequences, and fields is

programmable but limited by the number of registers.

The MODE registers allow the different fields to be

combined in any order for various readout configurations.

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