AD5372BCPZ datasheet(15/25 Pages) AD

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Preliminary Technical Data

AD5372/AD5373

Rev. P

rF | Page 15 of 25

gain required on the full output signal range.

Calculate the new maximum output range on VOUT

including the expected maximum offset and gain

errors.

Choose the new required VOUTmax and VOUTmin,

keeping the VOUT limits centered on the nominal

values. Note that VDD and VSS must provide sufficient

headroom.

Calculate the value of VREF as follows:

VREF = (VOUTMAX – VOUTMIN)/4

Reference Selection Example

Nominal Output Range = 12V (-4V to +8V)

Offset Error = ±70mV

Gain Error = ±3%

SIGGND = AGND = 0V

Gain Error = ±3%

=> Maximum Positive Gain Error = +3%

=> Output Range incl. Gain Error = 12 + 0.03(12)=12.36V

Offset Error = ±70mV

=> Maximum Offset Error Span = 2(70mV)=0.14V

=> Output Range including Gain Error and Offset Error =

12.36V + 0.14V = 12.5V

VREF Calculation

Actual Output Range = 12.5V, that is -4.25V to +8.25V

(centered);

VREF = (8.25V + 4.25V)/4 = 3.125V

If the solution yields an inconvenient reference level, the user

can adopt one of the following approaches:

Use a resistor divider to divide down a convenient,

higher reference level to the required level.

Select a convenient reference level above VREF and

modify the Gain and Offset registers to digitally

downsize the reference. In this way the user can use

almost any convenient reference level but may reduce

the performance by overcompaction of the transfer

function.

Use a combination of these two approaches

CALIBRATION

The user can perform a system calibration on the AD5372 and

AD5373 to reduce gain and offset errors to below 1 LSB. This is

achieved by calculating new values for the M and C registers and

reprogramming them.

Reducing Zero-scale and Full-scale Error

Zero-scale error can be reduced as follows:

Set the output to the lowest possible value.

Measure the actual output voltage and compare it with the

required value. This gives the zero-scale error.

Calculate the number of LSBs equivalent to the

error and subtract this from the default value of

the C register. Note that only negative zero-scale error can

be reduced.

Full-scale error can be reduced as follows:

Measure the zero-scale error.

Set the output to the highest possible value.

Measure the actual output voltage and compare it with the

required value. Add this error to the zero-scale error. This

is the full-scale error.

Calculate the number of LSBs equivalent to the full-scale

error and subtract it from the default value of the M

reduced.

The M and C registers should not be programmed until

both zero-scale and full-scale errors have been calculated.

AD5372 CALIBRATION EXAMPLE

This example assumes that a −4 V to +8 V output is required.

The DAC output is set to −4 V but measured at −4.03 V. This

gives an zero-scale error of −30 mV.

1 LSB = 12 V/65536 = 183.105 µV

30 mV = 164 LSB

164 LSB should be added to the default C register value:

(32768 + 164) = 32932

32932 should be programmed to the C register

The full-scale error can now be removed. The output is set to +8

V and a value of +8.02 V is measured. The full-scale error is

+20 mV – (–30 mV) = +50 mV

This is a full-scale error of +50 mV.

50 mV = 273 LSBs

273 LSB should be subtracted from the default M register

value: (65535 − 273) = 65262

65262 should be programmed to the M register

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