AD9381SLASHPCB datasheet(37/44 Pages) AD

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AD9381

Rev. 0 | Page 37 of 44

2-WIRE SERIAL CONTROL PORT

DATA TRANSFER VIA SERIAL INTERFACE

A 2-wire serial interface control is provided in the AD9381. Up

to two AD9381 devices can be connected to the 2-wire serial

interface, with a unique address for each device.

For each byte of data read or written, the MSB is the first bit of

the sequence. If the AD9381 does not acknowledge the master

device during a write sequence, the SDA remains high so the

master can generate a stop signal. If the master device does not

acknowledge the AD9381 during a read sequence, the AD9381

interprets this as the end of data. The SDA remains high so the

master can generate a stop signal.

The 2-wire serial interface comprises a clock (SCL) and a

bidirectional data (SDA) pin. The analog flat panel interface

acts as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled high by external pull-up resistors.

To write data to specific control registers of the AD9381, the 8-

bit address of the control register of interest must be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address auto-increments by 1 for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address

does not increment and remains at its maximum value. Any

base address higher than the maximum value does not produce

an acknowledge signal.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

There are six components to serial bus operation:

•

Start signal

•

Slave address byte

•

Base register address byte

•

Data byte to read or write

Data are read from the control registers of the AD9381 in a

similar manner. Reading requires two data transfer operations:

•

Stop signal

•

The base address must be written with the R/

•

Acknowledge (Ack)

W bit of the

slave address byte low to set up a sequential read

operation.

When the serial interface is inactive (SCL and SDA are high),

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slave devices that a data transfer sequence

is coming.

•

Reading (the R/W bit of the slave address byte high) begins

at the previously established base address. The address of

the read register auto-increments after each byte is

transferred.

The first 8 bits of data transferred after a start signal comprise a

7-bit slave address (the first 7 bits) and a single R/W

To terminate a read/write sequence to the AD9381, a stop signal

must be sent. A stop signal comprises a low-to-high transition

of SDA while SCL is high.

bit (the 8th

bit). The R/W bit indicates the direction of data transfer, read

from (1) or write to (0) the slave device. If the transmitted slave

address matches the address of the device (set by the state of the

SA0 input pin as shown in

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first genera-

ting a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial

interface lines.

Table 37), the AD9381 acknowledges

by bringing SDA low on the 9th SCL pulse. If the addresses do

not match, the AD9381 does not acknowledge.

Table 37. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

A6 (MSB)

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tDAH

tSTASU

tSTOSU

Figure 9. Serial Port Read/Write Timing

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