AD9396SLASHPCB datasheet(33/48 Pages) AD

33 / 48 page

AD9396

Rev. 0 | Page 33 of 48

0x1B—Bit[3] Clamp Disable

0 = internal clamp enabled. 1 = internal clamp disabled. The

power-up default is 0.

0x1B —Bits[2:1] Programmable Bandwidth

x0 = low bandwidth. x1 = high bandwidth. The power-up

default is 1.

0x1B—Bit[0] Hold Auto-Offset

0 = normal auto-offset operation. 1 = hold current offset value.

The power-up default is 0.

0x1C—Bit[7] Auto-Offset Enable

0 = manual offset. 1 = auto-offset using offset as target code.

The power-up default is 0.

0x1C—Bits[6:5] Auto-Offset Update Mode

00 = every clamp.

01 = every 16 clamps.

10 = every 64 clamps.

11 = every VSYNC.

The power-up default setting is 10.

0x1C—Bits[4:3] Difference Shift Amount

00 = 100% of difference used to calculate new offset.

01 = 50%.

10 = 25%.

11 = 12.5%.

The power-up default is 01.

0x1C—Bit[2] Auto-Jump Enable

0 = normal operation. 1 = if the code >15 codes off, the offset is

jumped to the predicted offset necessary to fix the >15 code

mismatch. The power-up default is 1.

0x1C—Bit[1] Post Filter Enable

The post filter reduces the update rate by 1/6 and requires that

all six updates recommend a change before changing the offset.

This prevents unwanted offset changes. 0 = disable post filter.

1 = enable post filter. The power-up default is 1.

0x1C—Bit[0] Toggle Filter Enable

The toggle filter looks for the offset to toggle back and forth and

holds it if triggered. This is to prevent toggling in case of

missing codes in the PGA. 1 = toggle filter on. 0 = toggle filter

off. The power-up default is 0.

0x1D—Bits[7:0] Slew Limit

Limits the amount the offset can change in a single update. The

power-up default is 0x08.

0x1E—Bits[7:0] Sync Filter Lock Threshold

This 8-bit register is programmed to set the number

of valid HSYNCs needed to lock the sync filter. This ensures

that a consistent, stable HSYNC is present before attempting to

filter. The power-up default setting is 32d.

0x1F—Bits[7:0] Sync Filter Unlock Threshold

This 8-bit register is programmed to set the number of missing

or invalid HSYNCs needed to unlock the sync filter. This

disables the filter operation when there is no longer a stable

HSYNC signal. The power-up default setting is 50d.

0x20—Bits[7:0] Sync Filter Window Width

This 8-bit register sets the distance in 40 MHz clock periods

(25 ns), which is the allowed distance for HSYNC pulses before

and after the expected HSYNC edge. This is the heart of the

filter in that it only looks for HSYNC pulses at a given time

(plus or minus this window) and then ignores extraneous

equalization pulses that disrupt accurate PLL operation. The

power-up default setting is 10d, or 200 ns on either side of the

expected HSYNC.

0x21—Bit[7] Sync Processing Filter Enable

This bit selects which HSYNC is used for the sync processing

functions of internal coast, H/V count, field detection, and

VSYNC duration counts. A clean HSYNC is fundamental to

accurate processing of the sync. 0 = sync processing uses raw

HSYNC or SOG. 1 = sync processing uses regenerated HSYNC

from sync filter. The power-up default setting is 1.

0x21—Bit[6] PLL Sync Filter Enable

This bit selects which signal the PLL uses. It can select between

raw HSYNC or SOG, or filtered versions. The filtering of the

HSYNC and SOG can eliminate nearly all extraneous

transitions which have traditionally caused PLL disruption. 0 =

PLL uses raw HSYNC or SOG inputs. 1 = PLL uses filtered

HSYNC or SOG inputs. The power-up default setting is 0.

0x21—Bit[5] VSYNC Filter Enable

The purpose of the VSYNC filter is to guarantee the position of

the VSYNC edge with respect to the HSYNC edge and to

generate a field signal. The filter works by examining the

placement of VSYNC and regenerating a correctly placed

VSYNC one line later. The VSYNC is first checked to see

whether it occurs in the Field 0 position or the Field 1 position.

This is done by checking the leading edge position against the

sync separator threshold and the HSYNC position. The HSYNC

width is divided into four quadrants with Quadrant 1 starting at

the HSYNC leading edge plus a sync separator threshold. If the

VSYNC leading edge occurs in Quadrant 1 or Quadrant 4, the

field is set to 0 and the output VSYNC is placed coincident with

the HSYNC leading edge. If the VSYNC leading edge occurs in

Quadrant 2 or Quadrant 3, the field is set to 1 and the output

VSYNC leading edge is placed in the center of the line. In this

way, the VSYNC filter creates a predictable relative position

between HSYNC and VSYNC edges at the output.

AD9396/PCB データシート(PDF) 33 Page - Analog Devices

AD9396/PCB データシート(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

データシートダウンロード