AD9396SLASHPCB datasheet(35/48 Pages) AD

35 / 48 page

AD9396

Rev. 0 | Page 35 of 48

0x25—Bits[5:4] Output Drive Strength

These two bits select the drive strength for all the high speed

digital outputs (except VSOUT, A0, and the O/E Field). Higher

drive strength results in faster rise times/fall times and makes it

easier to capture data. Lower drive strength results in slower

rise/fall times and helps to reduce EMI and digitally generated

power supply noise. The power-up default setting is 11.

Table 17. Output Drive Strength

Output Drive

Result

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

0x25—Bits[3:2] Output Mode

These bits choose between four options for the output mode,

one of which is exclusive to an HDMI input. 4:4:4 mode is

standard RGB; 4:2:2 mode is YCrCb, which reduces the number

of active output pins from 24 to 16; 4:4:4 is the double data rate

(DDR) output mode; and the data is RGB mode, but changes on

every clock edge. The power-up default setting is 00.

Table 18. Output Mode

Output

Mode

Result

4:4:4 RGB mode

4:2:2 YCrCb mode + DDR 4:2:2 on blue (secondary)

DDR 4:4:4: DDR mode + DDR 4:2:2 on blue

(secondary)

0x25—Bit[1] Primary Output Enable

This bit places the primary output in active or high impedance

mode. The primary output is designated when using either 4:2:2

or DDR 4:4:4. In these modes, the data on the red and green

output channels is the primary output, while the output data on

the blue channel (DDR YCrCb) is the secondary output. 0 =

primary output is in high impedance mode. 1 = primary output

is enabled. The power-up default setting is 1.

0x25—Bit[0] Secondary Output Enable

This bit places the secondary output in active or high

impedance mode. The secondary output is designated when

using either 4:2:2 or DDR 4:4:4. In these modes the data on the

blue output channel is the secondary output, while the output

data on the red and green channels is the primary output.

Secondary output is always a DDR YCrCb data mode. 0 =

secondary output is in high impedance mode. 1 = secondary

output is enabled. The power-up default setting is 0.

0x26—Bit[7] Output Three-State

When enabled, this bit puts all outputs (except SOGOUT) in a

high impedance state. 0 = normal outputs. 1 = all outputs

(except SOGOUT) in high impedance mode. The power-up

default setting is 0.

0x26—Bit[6] SOG Three-State

When enabled, this bit allows the SOGOUT pin to be placed in

a high impedance state. 0 = normal SOG output. 1 = SOGOUT

pin is in high impedance mode. The power-up default setting

is 0.

0x26—Bit[3] Power-Down Polarity

This bit defines the polarity of the input power-down pin.

0 = power-down pin is active low. 1 = power-down pin is active

high. The power-up default setting is 1.

0x26—Bits[2:1] Power-Down Pin Function

These bits define the different operational modes of the power-

down pin. These bits are functional only when the power-down

pin is active; when it is not active, the part is powered up and

functioning. The power-up default setting is 00.

Table 19. Power Down Pin Function

Function

Result

The chip is powered down and all outputs except

SOGOUT are in high impedance mode.

The chip is powered down and all outputs are in

high impedance mode.

The chip remains powered up, but all outputs

except SOGOUT are in high impedance mode.

The chip remains powered up, but all outputs are

in high impedance mode.

0x26—Bit[0] Power-Down

This bit is used to put the chip in power-down mode. In this

mode, the power dissipation is reduced to a fraction of the

typical power (see Table 1 for exact power dissipation). When in

power-down, the HSOUT, VSOUT, DATACK, and all 30 data

outputs are put into a high impedance state. Note that the

SOGOUT output is not put into high impedance. Circuit blocks

that continue to be active during power-down include the

voltage references, sync processing, sync detection, and the

serial register. These blocks facilitate a fast start-up from power-

down. 0 = normal operation. 1 = power-down. The power-up

default setting is 0.

0x27—Bit[7] Auto Power-Down Enable

This bit enables the chip to go into low power mode, or seek

mode if no sync inputs are detected. 0 = auto power-down

disabled. 1 = chip powers down if no sync inputs present. The

power-up default setting is 1.

0x27—Bit[6] HDCP A0 Address

This bit sets the LSB of the address of the HDCP I2C. This

should be set to 1 only for a second receiver in a dual-link

configuration. The power-up default is 0.

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