AD9398

Rev. 0 | Page 7 of 44

Pin Type

Pin No.

Mnemonic

Function

Value

POWER SUPPLY

80, 76, 72, 67, 45, 33

Analog Power Supply and DVI Terminators

3.3 V

100, 90, 10

Output Power Supply

1.8 V to 3.3 V

59, 56, 54

PLL Power Supply

1.8 V

48, 32, 30

Digital Logic Power Supply

1.8 V

GND

Ground

0 V

CONTROL

83

SDA

Serial Port Data I/O

3.3 V CMOS

82

SCL

Serial Port Data Clock

3.3 V CMOS

HDCP

49

DDCSCL

HDCP Slave Serial Port Data Clock

3.3 V CMOS

50

DDCSDA

HDCP Slave Serial Port Data I/O

3.3 V CMOS

51

MCL

HDCP Master Serial Port Data Clock

3.3 V CMOS

52

MDA

HDCP Master Serial Port Data I/O

3.3 V CMOS

AUDIO DATA OUTPUTS

28

S/PDIF

S/PDIF Digital Audio Output

27

26

25

24

20

MCLKIN

External Reference Audio Clock In

21

MCLKOUT

Audio Master Clock Output

22

SCLK

Audio Serial Clock Output

23

LRCLK

Data Output Clock for Left and Right Audio Channels

DATA ENABLE

88

DE

Data Enable

3.3 V CMOS

RTERM

46

RTERM

Sets Internal Termination Resistance

500 Ω

Table 6. Pin Function Descriptions

Mnemonic

Description

INPUTS

Rx0+

Digital Input Channel 0 True.

Rx0−

Digital Input Channel 0 Complement.

Rx1+

Digital Input Channel 1 True.

Rx1−

Digital Input Channel 1 Complement.

Rx2+

Digital Input Channel 2 True.

Rx2−

Digital input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

RxC+

Digital Data Clock True.

RxC−

Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

FILT

External Filter Connection.

For proper operation, the audio-clock generator PLL requires an external filter. Connect the filter shown in Figure 8

to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the

PCB Layout Recommendations section .

PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

OUTPUTS

HSOUT

Horizontal Sync Output.

A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can

be programmed via serial bus registers. By maintaining alignment with DATACK and DATA, data timing with

respect to horizontal sync can always be determined.

VSOUT

Vertical Sync Output.

The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this

output can be controlled via the serial bus bit (Register 0x24 [6]).

O/E FIELD

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is

odd or even. The polarity of this signal is programmable via Register 0x24[4].

DE

Data Enable that defines valid video. Can be received in the signal or generated by the AD9398.