CS4525 datasheet(49/91 Pages) CIRRUS

49 / 91 page

DS726A1

CS4525

6.2

Hardware Mode

A limited feature set is available when the CS4525 powers up in hardware mode. The available features are

described in the following sections. All device configuration is achieved via hardware control input pins.

6.2.1

System Clocking

In hardware mode, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK

pin. This input clock is used to synchronize the input serial audio signals with the internal clock domain

and to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used

to determine the sample rate of the serial audio input signals in order to automatically configure the vari-

ous internal filter coefficients.

To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied

SYS_CLK signal via the ClkFreq[1:0] hardware control pins. These pins must be set to the appropriate

level before the RST signal is released to initiate a power-up sequence. The nominal clock frequencies

indicated by the states of the ClkFreq[1:0] pins are shown in Table 10 below. See the SYS_CLK Switching

Specifications table on page 23 for complete input frequency range specifications.

Figure 12 below demonstrates a typical clocking configuration using the SYS_CLK input.

6.2.2

Power-Up and Power-Down

The CS4525 will remain in a completely powered-down state until the RST pin is brought high.

6.2.2.1

Recommended Power-Up Sequence

Hold RST low until the power supplies and the input SYS_CLK signal are stable.

Bring RST high.

Hardware mode will be entered after approximately 10 ms.

6.2.2.2

Recommended Power-Down Sequence

Bring MUTE low to mute the device’s outputs and minimize audible pops.

Bring RST low to halt the operation of the device.

The device’s power consumption will be brought to an absolute minimum.

Remove power.

ClkFreq1

ClkFreq0

Nominal SYS_CLK Frequency

Low

18.432 MHz

Low

High

24.576 MHz

High

Low

27.000 MHz

High

Reserved

Table 10. SYS_CLOCK Frequency Selection

SYS_CLK

RST

DSP

Reset_Out

Clock_In

Clock

XTI

XTO

Figure 21. Typical SYS_CLK Input Clocking Configuration

CS4525

CS4525 データシート(PDF) 49 Page - Cirrus Logic

CS4525 データシート(HTML) 49 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

データシートダウンロード

リンク URL

CS4525 データシート(PDF) 49 Page - Cirrus Logic

CS4525 データシート(HTML) 49 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

データシート ダウンロード

リンク URL

データシートダウンロード