CS4525 datasheet(44/91 Pages) CIRRUS

44 / 91 page

DS726A1

CS4525

The configurations are selected by the OutputCfg[1:0] bits in the Output Cfg register and must only be

changed when the device is in power-down mode (the PDnAll bit is set). Any attempt to write the Out-

putCfg[1:0] bits while the device is powered-up will be ignored.

It should be noted that signal on channels 1, 2, and 3 is dependent upon the digital sound processing

blocks being used. For instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way

crossover channel A high- and low-pass outputs respectively. For more information, see the Digital Sound

Processing section and Figure 14 on page 29.

6.1.7.2

PWM_SIG Logic-Level Output Configurations

Four channel mapping output configurations are supported for the PWM_SIG output pins as shown in

Table 8 below. The configurations support stereo, channel 1 with LFE, and channel 2 with LFE. When

disabled, the PWM_SIG pins continuously drive a logic ‘0’. The configurations are selected by the PW-

MDSel[1:0] bits in the Output Cfg register

To allow stereo headphone operation when the PWM logic-level outputs are mapped in a non-stereo out-

put configuration, if the HP_DETECT/MUTE pin is configured for headphone detection (the HP/Mute bit

is set), the PWM logic-level output mapping is affected by the active state of the headphone detection in-

put signal. In this configuration, the PWM_SIG1 and PWM_SIG2 output pins will output audio from

channel 1 and channel 2 respectively regardless of the setting of the PWMDSel[1:0] bits when the head-

phone detection input is active. When the headphone detection input signal becomes inactive, the PWM

logic-level outputs will be automatically reconfigured to the channel mapping dictated by the PWMD-

Sel[1:0] bits. See the Headphone Detection & Hardware Mute Input section on page 47 for more informa-

tion.

It should be noted that signal on channels 1, 2, and 3 is dependent upon the digital sound processing

blocks being used. For instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way

crossover channel A high- and low-pass outputs respectively. For more information, see the Digital Sound

Processing section and Figure 14 on page 29.

Referenced Control

OutputCfg[1:0]..................... “Output Configuration (OutputCfg[1:0])” on page 68

PDnAll ................................. “Power Down (PDnAll)” on page 81

PWMDSel[1:0]

PWM_SIG1

PWM_SIG2

Output disabled.

Channel 1

Channel 2

Channel 1

Channel 3

Channel 2

Channel 3

Table 8. PWM Logic-Level Output Configurations

Referenced Control

PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 68

HP/Mute .............................. “HP_Detect/Mute Pin Mode (HP/Mute)” on page 65

PDnAll ................................. “Power Down (PDnAll)” on page 81

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