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PEMD3_PIMD3_PUMD3

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Product data sheet

Rev. 11 — 25 September 2013

3 of 18

Nexperia

PEMD3; PIMD3; PUMD3

NPN/PNP resistor-equipped transistors

5.

Limiting values

[1]

Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

VCBO

collector-base voltage

open emitter

-

50

V

VCEO

collector-emitter voltage

open base

-

50

V

VEBO

emitter-base voltage

open collector

-

10

V

VI

input voltage TR1

positive

-

+40

V

negative

-

10

V

input voltage TR2

positive

-

+10

V

negative

-

40

V

IO

output current

-

100

mA

ICM

peak collector current

-

100

mA

Ptot

total power dissipation

Tamb  25 C

[1]

PEMD3 (SOT666)

-

200

mW

PIMD3 (SOT457)

-

250

mW

PUMD3 (SOT363)

-

200

mW

Per device

Ptot

total power dissipation

Tamb  25 C

[1]

PEMD3 (SOT666)

-

300

mW

PIMD3 (SOT457)

-

400

mW

PUMD3 (SOT363)

-

300

mW

Tj

junction temperature

-

150

C

Tamb

ambient temperature

65

+150

C

Tstg

storage temperature

65

+150

C