R03DS0149EJ0100 Rev.1.00

Page 1 of 7

2019.06.13

Datasheet

µPC813

High Slew Rate, Low Offset Voltage

J-FET Input Operational Amplifier

DESCRIPTION

μPC813 is a high-speed version of μPC811. The J-FET input operational amplifier features a high-speed PNP

transistor in the output stage for stable operation at a high slew rate of 25V/us with a gain of 1 (full feedback)

The resistor-trimming method proven in other Renesas High-Precision Op-Amp and High-Precision reference

voltage is incorporate in this Op-Amp input stage, thus producing an excellent low offset voltage characteristics

that has surpasses conventional general purpose op-amp in spite of being JFET input.

Under the same series, μPC814, 4094 with the same circuit configuration are also available.

FEATURES

 Input Offset Voltage

±1 mV (TYP.) (±2.5 mV MAX.)

 VIO Temperature Drift

±7 µV/

C (TYP.)

 Input Bias Current

50 pA (TYP.)

 Slew Rate

25 V/µs (TYP.)

 Unity Gain Frequency

6 MHz (TYP.)

 Input Equivalent Noise Voltage Density

19 nV/ Hz (TYP.) (f = 1 kHz)

 Stable operation against capacitive load

(Capacitive Load at 220 pF, AV = +1 )

 Built-In Phase Compensation Circuit

 Built-In Output Short Circuit Protection

 Standard Single Op-Amp terminal connection (pin compatible)

ORDERING INFORMATION

Ordering Name

Package

μPC813G2-A

8-pin plastic SOP ( 225 mil)

EQUIVALENT CIRCUIT

PIN CONFIGURATION (Top View)

TRIMMED

OFFSET

NULL

OFFSET

NULL

HIGH SPEED

PNP

Q3

Q4

Q1

Q2

Q5

Q8

Q10

Q9

Q6

Q7

C1

D1

IN

II

(2)

(3)

(1)

(5)

(7)

(6)

(4)

V +

V -

OUT

1

OFFSET

NULL

6

V +

II 2

IN

V -

8

OUT

7

4

3

NC

OFFSET

NULL

-+

5

µPC813G2

備考

NC : No Connection

R03DS0149EJ0100

Rev.1.00

2019.06.13

Note