CS5535 datasheet(94/555 Pages) NSC

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4.5

UNIVERSAL SERIAL BUS CONTROLLER

The two Universal Serial Bus Controllers (USBC) each

contain a GeodeLink Adapter, PCI Adapter, and USB Core

blocks. The functional descriptions of the blocks are

described in the following sub-sections.

4.5.1

GeodeLink Adapter

The GeodeLink Adapter (GLA) translates GeodeLink trans-

actions to/from Local bus transactions. The GLA interfaces

to a 64-bit GLIU (GeodeLink Interface Unit) and a 32-bit

Local bus. The GLA supports in-bound memory and I/O

requests which are converted by the PCI Adapter (PA) into

PCI memory and I/O requests that target the USBC. It also

supports in-bound MSR transactions to the MSRs. These

are located “between” the GLA and PA. Lastly, there is a

special MSR used to pass PCI configuration requests to

the PA. The GLA supports out-bound memory requests

only. I/O and MSR transactions from the USBC never

occur. USBC PCI master requests are converted by the PA

into Local bus master requests. These requests may con-

sist of a simple 4-byte read or write. Alternatively, a PCI

burst transaction of any length may be converted to an

appropriate series of GLIU transactions by the GLA. Lastly,

the GLA synchronizes GLIU transactions at the GLIU clock

to the slower Local bus transaction at Local bus clock.

4.5.2

PCI Adapter

The PCI Adapter translates PCI signals to a specific Local

bus transaction that is attached to the GLA, while the PCI

signals are connected directly to a compatible PCI device.

It also translates the Local bus transactions to PCI transac-

tions.

4.5.3

USB Core

The USB Core is a PCI-based implementation of the Uni-

versal Serial Bus (USB) v1.1 Specification utilizing the

Open Host Controller Interface (OHCI) standard developed

by Compaq, Microsoft, and National Semiconductor. The

USB Core consists of the following three blocks:

• Host Controller

• USB Interface

• PCI Interface

The USB Core block diagram is shown in Figure 4-8.

Figure 4-8. USB Core Block Diagram

USB Port 1

Port 1

Port 2

Root

Hub

Control

SIE

USB Port 2

Data Buffer

Clock

Generator

Bus

Master

List

Processor

Interrupts

Frame Mgmnt

PCI I/O

PCI Slave

PCI Config

PCI Master

PCI

Host Controller

USB

Interface

Embedded PCI Bus

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