CS5535 datasheet(15/555 Pages) NSC

15 / 555 page

Revision 0.8

www.national.com

Architecture Overview (Continued)

Versatile input filtering is available for each GPIO input.

Each preliminary input is optionally connected to a digital

filter circuit that is optionally followed by an event counter.

Lastly followed by an edge detector that together provide

eight different ICFs (input conditioning functions), plus an

auto-sense feature for determining the initial condition of

the pin.

1.6.9

Multi-Function General Purpose Timers

This module contains eight Multi-Function General Pur-

pose Timers (MFGPTs), six are in the normal VDD Working

power domain, while the other two are in the Standby

power domain. The timers are very versatile and can be

configured to provide a Watchdog timer (trigger GPIO out-

put, interrupt or reset), perform Pulse Width Modulation

(PWM) or Pulse Density Modulation (PDM), create Blink

(low frequency pulse for LED), generate GPIO outputs, or

act as general purpose timers.

Each MFGPT operates independently and has the follow-

ing features:

• 32 kHz or 14.318 MHz clock selectable by software

(applies to MFGPT0 to MFGPT5, in Working power

domain, only).

• MFGPT6 and MFGPT7, in Standby power domain, use

32 kHz clock.

• Programmable input clock prescaler divisor to divide

input clock by 2i, where i = 0 to 15.

• Provide outputs for generating reset (limited to MFGPT0

to MFGPT5), IRQs, NMI, and ASMIs (indirectly through

PICs).

1.6.10 Flash Interface

The CS5535 has a Flash device interface that supports

popular NOR Flash and inexpensive NAND Flash devices.

This interface is shared with the IDE interface (ATA-5 Con-

troller (ATAC)), using the same balls. NOR or NAND Flash

may co-exist with IDE devices using PIO (Programmed

I/O) mode. The 8-bit interface supports up to four “lanes” of

byte-wide Flash devices through use of four independent

chip selects, and allows for booting from the array. Hard-

ware support is present for SmartMedia-type ECC (Error

Correction Code) calculations, off-loading software from

having to support this task.

All four independent chip selects may be used as general

purpose chip selects to support other ISA-like slave

devices. Up to 1 kB of address space (without external

latches) may be supported using these signals.

1.6.11 Real-Time Clock with CMOS RAM

The CS5535 maintains a real-time clock for system use.

The clock is powered by an external battery and so contin-

ues to keep accurate time even when system power is

removed. The clock can be set to make automatic Daylight

Savings Time changes in the spring and fall without user

intervention. There are separate registers for seconds,

minutes, hours, days (both day of the week and day of the

month), months, and years. Alarms can be set for any time

within the range of these registers, which have a 100-year

capability. The clock uses an external 32 kHz oscillator or

crystal as the timing element.

The same battery that keeps the clock continuously pow-

ered also provides power to a block of 242 bytes of CMOS

RAM, used for storing non-volatile system parameters.

1.6.12 Power Management Controller

The CS5535 has state-of-the-art power management

capabilities designed into every module. Independent clock

controls automatically turn clocks off to sections of the chip

that are not being used, saving considerable power. In

addition, the chip supports full Sleep and Wakeup states

with multiple methods of inducement. A suite of external

signals support power management of devices on the sys-

tem board. Legacy Power Management (PM), Advanced

Power Management (APM), and Advanced Configuration

and Power Interface (ACPI) techniques and requirements

are supported. The GPIO subsystem can be configured to

transmit any of several wakeup events into the system.

The CS5535 is divided into two main power domains:

Working and Standby, plus circuits such as the real-time

clock and CMOS RAM that are battery-backed. Most of the

CS5535 is in the Working power domain, except for

GPIO[31:24] and MFGPT[7:6]. This allows these devices to

be used for wakeup events or output controls.

1.7

GEODELINK INTERFACE UNIT

The GeodeLink Interface Unit (GLIU) makes up the internal

bus derived from the GeodeLink architecture. It has eight

ports, one of which is dedicated to itself, leaving seven for

use by internal GeodeLink devices. Figure 1-1 "Internal

Block Diagram" on page 12 shows this device as the cen-

tral element of the architecture, though its presence is basi-

cally transparent to the end user.

1.8

LOW VOLTAGE DETECT

The Low Voltage Detect (LVD) circuit monitors: Standby I/O

voltage, Standby Core voltage, and Working Core voltage.

Working I/O voltage is not monitored and is assumed to

track with Working Core voltage. The LVD monitors these

voltages to provide Working and Standby power-good sig-

nals (resets) for the respective working and standby power

domains. Additionally, the PMC monitors the working

power-good signal to shut-down and/or re-start the system

as appropriate.

CS5535 データシート(PDF) 15 Page - National Semiconductor (TI)

CS5535 データシート(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード