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STE100A データシート(PDF) 30 Page - STMicroelectronics |
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STE100A データシート(HTML) 30 Page - STMicroelectronics |
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30 / 82 page ![]() Registers and descriptors description STE10/100A 30/82 4 Registers and descriptors description Note: There are three kinds of registers within the STE10/100A: STE10/100A configuration registers, PCI control/status registers, and transceiver control/status registers. The STE10/100A configuration registers are used to initialize and configure the STE10/100A and for identifying and querying the STE10/100A. The PCI control/status registers are used to communicate between the host and STE10/100A. The host can initialize, control, and read the status of the STE10/100A through mapped I/O or memory address space. The STE10/100A contains 11 16-bit registers to supported transceiver control and status. They include 7 basic registers which are defined according to clause 22 “Reconciliation Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. The STE10/100A also provides receive and transmit descriptors for packet buffering and management. 4.1 STE10/100A configuration registers An STE10/100A software driver can initialize and configure the chip by writing its configuration registers. The contents of configuration registers are set to their default values upon power-up or whenever a hardware reset occurs, but their settings remain unchanged whenever a software reset occurs. The configuration registers are byte, word, and double word accessible. Table 4. STE10/100A configuration registers list Offset Index Name Description 00h CR0 LID Loaded device ID and vendor ID 04h CR1 CSC Configuration status and command 08h CR2 CC Class code and revision number 0ch CR3 LT Latency timer 10h CR4 IOBA IO base address 14h CR5 MBA Memory base address 2ch CR11 SID Subsystem ID and vendor ID 30h CR12 BRBA Boot ROM base address (ROM size = 128Kbit) 34h CR13 CP Capability pointer 3ch CR15 CINT Configuration interrupt 40h CR16 DS Driver space for special purpose 80h CR32 SIG Signature of STE10/100A c0h CR48 PMR0 Power management register 0 c4h CR49 PMR1 Power management register 1 |
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