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STE100A データシート(PDF) 32 Page - STMicroelectronics

部品番号 STE100A
部品情報  PCI 10/100 Ethernet controller with integrated PHY (3.3V)
PDF  82 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE100A データシート(HTML) 32 Page - STMicroelectronics

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Registers and descriptors description
STE10/100A
32/82
4.1.1
STE10/100A configuration registers description
Table 6.
Configuration registers description
Bit #
Name
Description
Default
RW type
CR0 (offset = 00h), LID - Loaded identification number of device and vendor
31~16
LDID
Loaded device ID, the device ID number loaded from
serial EEPROM
From
EEPROM
R/O
15~0
LVID
Loaded vendor ID, the vendor ID number loaded
from serial EEPROM
From
EEPROM
R/O
From EEPROM: Loaded from EEPROM
CR1 (offset = 04h), CSC - Configuration command and status
31
SPE
Status parity error.
1: means that STE10/100A detected a parity error.
This bit will be set even if the parity error response
(bit 6 of CR1) is disabled.
0R/W
30
SES
Status system error.
1: means that STE10/100A asserted the system
error pin.
0R/W
29
SMA
Status master abort.
1: means that STE10/100A received a master abort
and has terminated a master transaction.
0R/W
28
STA
Status target abort.
1: means that STE10/100A received a target abort
and has terminated a master transaction.
0R/W
27
---
Reserved
26, 25
SDST
Status device select timing. Indicates the timing of
the chip’s assertion of device select.
01: indicates a medium assertion of DEVSEL#.
01
R/O
24
SDPR
Status data parity report.
1: when three conditions are met:
a. STE10/100A asserted parity error (PERR#) or it
detected parity error asserted by another device.
b. STE10/100A is operating as a bus master.
c. STE10/100A’s parity error response bit (bit 6 of
CR1) is enabled.
0R/W
23
SFBB
Status fast back-to-back.
Always 1, since STE10/100A has the ability to
accept fast back to back transactions.
1R/O
22~21
---
Reserved



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