AD7621 datasheet(24/32 Pages) AD

24 / 32 page

AD7952

Rev. 0 | Page 24 of 32

INTERFACES

DIGITAL INTERFACE

The AD7952 has a versatile digital interface that can be set up

as either a serial or a parallel interface with the host system. The

serial interface is multiplexed on the parallel data bus. The AD7952

digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In

most applications, the OVDD supply pin is connected to the host

system interface 2.5 V to 5.25 V digital supply. Finally, by using

the OB/2C input pin, both twos complement or straight binary

coding can be used.

Two signals, CS and RD, control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7952 in

multicircuit applications and is held low in a single AD7952

design. RD is generally used to enable the conversion result on

the data bus.

RESET

The RESET input is used to reset the AD7952. A rising edge on

RESET aborts the current conversion (if any) and tristates the

data bus. The falling edge of RESET resets the AD7952 and

clears the data bus and configuration register. See Figure 35 for

the RESET timing details.

RESET

DATA

BUS

BUSY

CNVST

Figure 35. RESET Timing

PARALLEL INTERFACE

The AD7952 is configured to use the parallel interface when

SER/PAR is held low.

Master Parallel Interface

Data can be continuously read by tying CS and RD low, thus

requiring minimal microprocessor connections. However, in

this mode, the data bus is always driven and cannot be used in

shared bus applications (unless the device is held in RESET).

Figure 36 details the timing for this mode.

BUSY

DATA

BUS

PREVIOUS CONVERSION DATA

NEW DATA

CNVST

CS = RD = 0

t10

t11

Figure 36. Master Parallel Data Timing for Reading (Continuous Read)

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after

each conversion, which is during the next acquisition phase, or

during the following conversion, as shown in Figure 37 and

Figure 38, respectively. When the data is read during the conver-

sion, it is recommended that it is read-only during the first half

of the conversion phase. This avoids any potential feedthrough

between voltage transients on the digital interface and the most

critical analog conversion circuitry.

CURRENT

CONVERSION

t13

t12

BUSY

DATA

BUS

Figure 37. Slave Parallel Data Timing for Reading (Read After Convert)

CONVERSION

t13

t12

BUSY

DATA

BUS

CNVST,

CS = 0

Figure 38. Slave Parallel Data Timing for Reading (Read During Convert)

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