AD7621 datasheet(28/32 Pages) AD

28 / 32 page

AD7952

Rev. 0 | Page 28 of 32

External Clock Data Read After/During Conversion

It is also possible to begin to read data after conversion and

continue to read the last bits after a new conversion is initiated.

This method allows the full throughput and the use of a

slower SDCLK frequency. Again, it is recommended to use a

discontinuous SDCLK whenever possible to minimize potential

incorrect bit decisions. For the different modes, the use of a

slower SDCLK, such as 20 MHz in warp mode, 15 MHz in

normal mode, and 13 MHz in impulse mode can be used.

SDIN

SDOUT

BUSY

EXT/INT = 1 INVSCLK = 0

SDCLK

SER/PAR = 1

RD = 0

D13

D12

D11

X13

X12

X13

X12

X11

Y13

Y12

t31

t32

t16

t33

t34

t37

t35

t36

*A DISCONTINUOUS SDCLK IS RECOMMENDED.

Figure 43. Slave Serial Data Timing for Reading (Read After Convert)

SDOUT

BUSY

EXT/INT = 1

INVSCLK = 0

SDCLK

SER/PAR = 1

RD = 0

D13

D12

t31

t32

t16

t37

t35

t36

CNVST

t27

*A DISCONTINUOUS SDCLK IS RECOMMENDED.

DATA = SDIN

Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

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