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CS51313

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regulator output voltage will follow it, less the 1.1 V PWM

offset, until it achieves the voltage programmed by the

DAC’s VID input. The Error Amp will then source or sink

current to the COMP cap as required to maintain the correct

regulator DC output voltage. Since the rate of increase of the

COMP pin voltage is typically set much slower than the

regulator’s slew capability, inrush current, output voltage,

and duty cycle all gradually increase from zero. (See Figures

10, 11, and 12).

Figure 10. Normal Startup (2.0 ms/div)

Channel 1 − Regulator Output Voltage (1.0 V/div)

Channel 2 − COMP Pin (1.0 V/div)

Channel 3 − VCC (10 V/div)

Channel 4 − Regulator Input Voltage (5.0 V/div)

Figure 11. Normal Startup Showing Initial Pulse

Followed by Soft Start (20 ms/div)

Channel 1 − Regulator Output Voltage (0.2 V/div)

Channel 2 − Inductor Switching Node (5.0 V/div)

Channel 3 − VCC (10 V/div)

Channel 4 − Regulator Input Voltage (5.0 V/div)

Figure 12. Pulse−By−Pulse Regulation During Soft

Start (2.0 ms/div)

Channel 1 − Regulator Output Voltage (0.2 V/div)

Channel 2 − Inductor Switching Node (5.0 V/div)

Channel 3 − VCC (10 V/div)

Channel 4 − Regulator Input Voltage (5.0 V/div)

If the voltage across the Current Sense resistor generates a

voltage difference between the VFB and VOUT pins that

exceeds the OVC Comparator Offset Voltage (86 mV typical),

the Fault latch is set. This causes the COMP pin to be quickly

discharged, turning off GATE(H) and the upper NFET since

the voltage on the COMP pin is now less than the 1.1 V PWM

comparator offset. The Fault latch is reset when the voltage on

the COMP decreases below the discharge threshold voltage

(0.25 V typical). The COMP capacitor will again begin to

charge, and when it exceeds the 1.1 V PWM comparator offset,

the regulator output will Soft Start normally (see Figure 13).

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