CS51313 datasheet(13/23 Pages) ONSEMI

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CS51313

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Response, a combination of a number of high frequency and

bulk output capacitors are usually used.

Slope Compensation

The V2 control method uses a ramp signal, generated by

the ESR of the output capacitors, that is proportional to the

ripple current through the inductor. To maintain regulation,

the V2 control loop monitors this ramp signal, through the

PWM comparator, and terminates the switch on−time.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope presented to the PWM

comparator, due to the very low ESR, can lead to pulse width

jitter and variation caused by both random or synchronous

noise.

Adding slope compensation to the control loop, avoids

erratic operation of the PWM circuit, particularly at lower

duty cycles and higher frequencies, where there is not

enough ramp signal, and provides a more stable switchpoint.

The scheme that prevents that switching noise

prematurely triggers the PWM circuit consists of adding a

positive voltage slope to the output of the Error Amplifier

(COMP pin) during an off−time cycle.

The circuit that implements this function is shown in

Figure 14.

Figure 14. Small RC Filter Provides the

Proper Voltage Ramp at the Beginning of

Each On−Time Cycle

To Synchronous FET

CCOMP

CS51313

COMP

GATE(L)

The ramp waveform is generated through a small RC filter

that provides the proper voltage ramp at the beginning of

each on−time cycle. The resistors R1 and R2 in the circuit of

Figure 14 form a voltage divider from the GATE(L) output,

superimposing a small artificial ramp on the output of the

error amplifier. It is important that the series combination

R1/R2 is high enough in resistance not to load down and

negatively affect the slew rate on the GATE(L) pin.

PROTECTION AND MONITORING FEATURES

Overcurrent Protection

A loss−less hiccup mode current limit protection feature

is provided, requiring only the COMP capacitor to

implement. The CS51313 provides overcurrent protection

by sensing the current through a “Droop” resistor, using an

internal current sense comparator. The comparator

compares the voltage drop across the “Droop” resistor to an

internal reference voltage of 86 mV (typical).

If the voltage drop across the “Droop” resistor exceeds

this threshold, the current sense comparator allows the fault

latch to be set. This causes the regulator to stop switching.

During this over current condition, the CS51313 stays off

for the time it takes the COMP pin capacitor to discharge to

its lower 0.25 V threshold. As soon as the COMP pin reaches

0.25 V, the Fault latch is reset (no overcurrent condition

present) and the COMP pin is charged with a 30 μA current

source to a voltage 1.1 V greater than the VFB voltage. Only

at this point the regulator attempts to restart normally. The

CS51313 will operate initially with a duty cycle whose value

depends on how low the VFB voltage was during the

overcurrent condition (whether hiccup mode was due to

excessive current or hard short). This protection scheme

minimizes thermal stress to the regulator components, input

power supply, and PC board traces, as the over current

condition persists. Upon removal of the overload, the fault

latch is cleared, allowing normal operation to resume.

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the

normal operation of the V2 control topology and requires no

additional external components. The control loop responds

to an overvoltage condition within 200 ns, causing the top

MOSFET to shut off, disconnecting the regulator from its

input voltage. This results in a “crowbar” action to clamp the

output voltage and prevents damage to the load. The

regulator will remain in this state until the overvoltage

condition ceases or the input voltage is pulled low.

Additionally, a dedicated Overvoltage protection (OVP)

output pin (pin 13) is provided in the CS51313. The OVP

signal will go high (overvoltage condition), if the output

voltage (VCC(CORE)) exceeds the regulation voltage by

8.5% of the voltage set by the particular DAC code. The

OVP pin can source up to 25 mA of current that can be used

to drive an SCR to crowbar the power supply.

Power Good Circuit

The Power Good pin (pin 14) is an open−collector signal

consistent with TTL DC specifications. It is externally

pulled up, and is pulled low (below 0.3 V) when the

regulator output voltage typically exceeds ±8.5% of the

nominal output voltage. Maximum output voltage deviation

before Power Good is pulled low is ±12%.

Output Enable

On/off control of the regulator outputs can be

implemented by pulling the COMP pins low. It is required

to pull the COMP pins below the 1.1 V PWM comparator

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