SST25VF080B datasheet(7/33 Pages) MICROCHIP

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DS20005045D-page 7

SST25VF080B

4.4

Instructions

Instructions are used to read, write (Erase and Pro-

gram), and configure the SST25VF080B. The instruc-

tion bus cycles are 8 bits each for commands (Op

Code), data, and addresses. Prior to executing any

Byte Program, Auto Address Increment (AAI) program-

ming, Sector Erase, Block Erase, Write STATUS Reg-

ister, or Chip Erase instructions, the Write Enable

(WREN) instruction must be executed first. The com-

plete list of instructions is provided in Table 4-4. All

instructions are synchronized off a high to low transition

of CE#. Inputs will be accepted on the rising edge of

SCK starting with the most significant bit. CE# must be

driven low before an instruction is entered and must be

driven high after the last bit of the instruction has been

shifted in (except for Read, Read-ID, and Read STA-

TUS Register instructions). Any low to high transition

on CE#, before receiving the last bit of an instruction

bus cycle, will terminate the instruction in progress and

return the device to standby mode. Instruction com-

mands (Op Code), addresses, and data are all input

from the most significant bit (MSb) first.

TABLE 4-4:

DEVICE OPERATION INSTRUCTION

Instruction

Description

Op Code Cycle(1)

Address

Cycle(s)(2)

Dummy

Cycle(s)

Data

Cycle(s)

Read

Read Memory

0000 0011b (03H)

1 to ∞

High-Speed Read

Read Memory at higher speed

0000 1011b (0BH)

1 to ∞

4-Kbyte Sector Erase(3) Erase 4 Kbyte of memory array 0010 0000b (20H)

32-Kbyte Block Erase(4) Erase 32 Kbyte block of

memory array

0101 0010b (52H)

64-Kbyte Block Erase(5) Erase 64 Kbyte block of

memory array

1101 1000b (D8H)

Chip-Erase

Erase Full Memory Array

0110 0000b (60H) or

1100 0111b (C7H)

Byte Program

To Program One Data Byte

0000 0010b (02H)

AAI Word Program(6)

Auto Address Increment

Programming

1010 1101b (ADH)

2 to ∞

RDSR(7)

Read STATUS Register

0000 0101b (05H)

1 to ∞

EWSR

Enable Write STATUS Register 0101b 0000b (50H)

WRSR

Write STATUS Register

0000 0001b (01H)

WREN

Write Enable

0000 0110b (06H)

WRDI

Write Disable

0000 0100b (04H)

RDID(8)

Read-ID

1001 0000b (90H) or

1010 1011b (ABH)

1 to ∞

JEDEC-ID

JEDEC ID read

1001 1111b (9FH)

3 to ∞

EBSY

Enable SO to output RY/BY#

status during AAI programming

0111 0000b (70H)

DBSY

Disable SO as RY/BY# status

during AAI programming

1000 0000b (80H)

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