| データシートサーチシステム |
|
SST25VF080B データシート(PDF) 9 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
SST25VF080B データシート(HTML) 9 Page - Microchip Technology |
|
9 / 33 page ![]() 2005-2020 Microchip Technology Inc. DS20005045D-page 9 SST25VF080B 4.4.2 HIGH-SPEED READ (66 MHZ)1 The High-Speed Read instruction, supporting up to 66 MHz Read, is initiated by executing an 8-bit com- mand, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active-low for the dura- tion of the High-Speed Read cycle. See Figure 4-4 for the High-Speed Read sequence. Following a dummy cycle, the High-Speed Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wrap-around) of the address space. Once the data from address location FFFFFH has been read, the next output will be from address location 00000H. FIGURE 4-4: HIGH-SPEED READ SEQUENCE 4.4.3 BYTE PROGRAM The Byte Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Pro- gram operation. A Byte Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE# must remain active-low for the duration of the Byte Program instruc- tion. The Byte Program instruction is initiated by exe- cuting an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSb (bit 7) to LSb (bit 0). CE# must be driven high before the instruction is executed. The user may poll the BUSY bit in the software STATUS Register or wait TBP for the completion of the internal self-timed Byte Program operation. See Figure 4-5 for the Byte Program sequence. FIGURE 4-5: BYTE PROGRAM SEQUENCE Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) CE# SO SI SCK ADD. 012 34 5 6 7 8 ADD. ADD. 0B High-Impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSb MS MSb MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT CE# SO SI SCK ADD. 0 1 234 5 6 78 ADD. ADD. DIN 02 MS H I 15 16 23 24 31 32 39 MODE 0 MODE 3 MS MS LS |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |