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WM8960GEFL/V データシート(PDF) 21 Page - Wolfson Microelectronics plc |
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WM8960GEFL/V データシート(HTML) 21 Page - Wolfson Microelectronics plc |
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21 / 88 page ![]() Preliminary Technical Data WM8960 w PTD, September 2006, Rev 2.0 21 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8 IPVU N/A Input PGA Volume Update Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) 7 LINMUTE 1 Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. 6 LIZC 0 Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately R0 (00h) Left Channel PGA 5:0 LINVOL [5:0] 010111 ( 0dB ) Left Input PGA Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB 8 IPVU N/A Input PGA Volume Update Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) 7 RINMUTE 1 Right Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. 6 RIZC 0 Right Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately R1 (01h) Right Channel PGA 5:0 RINVOL [5:0] 010111 ( 0dB ) Right Input PGA Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB 0 TOEN 0 Timeout Enable (Also enables jack detect debounce clock) 0 = Timeout disabled 1 = Timeout enabled R23 (17h) Additional Control (1) 1 TOCLKSEL 0 Slow Clock Selection (Used for volume update timeouts and for jack detect debounce) 0 = SYSCLK / 2 21 (Slower Response) 1 = SYSCLK / 2 19 (Faster Response) Table 4 Input PGA Volume Control See "Volume Updates" for more information on volume update bits, zero cross and timeout operation. LINE INPUTS Two pairs of stereo line inputs (LINPUT2 / RINPUT2 and LINPUT3 / RINPUT3) are available as analogue inputs into the ADC path. LINPUT3 and RINPUT3 can also be input directly to the output mixers via the bypass paths. See "Output Signal Path" for more information on the bypass paths. |
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