UJA1069 datasheet(20/64 Pages) PHILIPS

20 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

20 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.7.3 Termination control

The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75

µA;

see Figure 11.

During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN

provides an internal switch to BAT42. For master and slave operation an external resistor,

Ω or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external

diode in series with the termination resistor is not required due to the incorporated internal

diode.

6.7.4 LIN slope control

The LSC bit in the Physical Layer Control register offers a choice between two LIN slope

times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).

Fig 10. LIN wake-up timing diagram

001aad447

tBUS(LIN)

LIN

wake-up

Fig 11. States of the RTLIN pin

001aad183

RTLIN = OFF

power-on

RTLIN = ON

supplied directly

out of BAT42

RTLIN = 75

µA

supplied directly

out of BAT42

Off-line mode

AND receiver dominant

> tLIN(dom)(det)

Off-line mode

AND receiver recessive

> tLIN(dom)(rec)

Active mode and receiver recessive

> tLIN(dom)(rec)

OR mode change to Active mode

Active mode and receiver dominant

> tLIN(dom)(det)

OR Off-line mode

mode change to Active mode

UJA1069 データシート(PDF) 20 Page - NXP Semiconductors

UJA1069 データシート(HTML) 20 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

データシートダウンロード