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M49000000P データシート(PDF) 62 Page - Advanced Micro Devices |
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M49000000P データシート(HTML) 62 Page - Advanced Micro Devices |
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62 / 64 page ![]() July 19, 2002 Am49DL32xBG 61 P R E L I M I NARY pSRAM ADDRESS SKEW Figure 35. Read Address Skew Note: If multiple invalid address cycles shorter than t RC min occur for a period greater than 10 µs, at least one valid address cycle over t RC min is required during that period. Figure 36. Write Address Skew Note: If multiple invalid address cycles shorter than t WC min occur for a period greater than 10 µs, at least one valid address cycle over t WC min, in addition to tWP min, is required during that period. CE#1 WE# Address tRC min over 10 µs CE#1 WE# Address tWP min tWC min over 10 µs |
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