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ams Datasheet

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[v1-01] 2018-Apr-23

TSL2561 − Principles of Operation

Control Register (0h)

The Control Register contains two bits and is primarily used to

power the TSL2561 device up and down as shown in Figure 16.

Figure 16:

Control Register

Note(s):

1. If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be used to verify that the device is

communicating properly.

Timing Register (1h)

The Timing Register controls both the integration time and the

gain of the ADC channels. A common set of control bits is

provided that controls both ADC channels. The Timing Register

defaults to 02h at power on.

Figure 17:

Timing Register

Note(s):

1. This field only has meaning when INTEG = 11. It is ignored at all other times.

7

6

5432

10

Resv

Resv

Resv

Resv

Resv

Resv

POWER

Field

Bit

Description

Resv

7:2

Reserved. Write as 0.

POWER

1:0

Power up/power down. By writing a 03h to this register, the device is powered up.

By writing a 00h to this register, the device is powered down(1).

7

6

5432

10

Resv

Resv

Resv

GAIN

Manual

Resv

INTEG

Field

Bit

Description

Resv

7:5

Reserved. Write as 0.

GAIN

4

Switches gain between low gain and high gain modes. Writing a 0 selects low gain

(1×); writing a 1 selects high gain (16×).

Manual

3

Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an

integration cycle(1)

Resv

2

Reserved. Write as 0.

INTEG

1:0

Integrate time. This field selects the integration time for each conversion.