TSL2561 datasheet(22/37 Pages) OSRAM

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ams Datasheet

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[v1-01] 2018-Apr-23

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TSL2561 − Principles of Operation

ADC Channel Data Registers (Ch − Fh)

The ADC channel data are expressed as 16-bit values spread

across two registers. The ADC channel 0 data registers,

DATA0LOW and DATA0HIGH provide the lower and upper bytes,

respectively, of the ADC value of channel 0. Registers

DATA1LOW and DATA1HIGH provide the lower and upper bytes,

respectively, of the ADC value of channel 1. All channel data

registers are read-only and default to 00h on power up.

Figure 24:

ADC Channel Data Registers

The upper byte data registers can only be read following a read

to the corresponding lower byte register. When the lower byte

The upper register will read the correct value even if additional

ADC integration cycles end between the reading of the lower

and upper registers.

Note(s): The Read Word protocol can be used to read

byte-paired registers. For example, the DATA0LOW and

DATA0HIGH registers (as well as the DATA1LOW and DATA1HIGH

registers) may be read together to obtain the 16-bit ADC value

in a single transaction.

Address

Bits

Description

DATA0LOW

7:0

ADC channel 0 lower byte

DATA0HIGH

7:0

ADC channel 0 upper byte

DATA1LOW

7:0

ADC channel 1 lower byte

DATA1HIGH

7:0

ADC channel 1 upper byte

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