HCS08 datasheet(185/290 Pages) MOTOROLA

185 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

185

MC9S08GB/GT

When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle,

or queued break character finishes transmitting before allowing the pin to revert to a general-purpose

I/O pin.

RE — Receiver Enable

When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin.

1 = Receiver on.

0 = Receiver off.

RWU — Receiver Wakeup Control

This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic

hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between

messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character

(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected

hardware condition automatically clears RWU. Refer to 11.6.3 Receiver Wakeup Operation for

more details.

1 = SCI receiver in standby waiting for wakeup condition.

0 = Normal SCI receiver operation.

SBK — Send Break

Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break

characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of

the set and clear of SBK relative to the information currently being transmitted, a second break

character may be queued before software clears SBK. Refer to 11.5.2 Send Break and Queued Idle

for more details.

1 = Queue break character(s) to be sent.

0 = Normal transmitter operation.

11.10.4 SCI x Status Register 1 (SCIxS1)

This register has eight read-only status flags. Writes have no effect. Special software sequences (which do

not involve writing to this register) are used to clear these status flags.

Figure 11-9 SCI x Status Register 1 (SCIxS1)

Bit 7

654321

Bit 0

Read:

TDRE

RDRF

IDLE

Write:

Reset:

11000000

= Unimplemented or Reserved

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