MPC885ZP80 datasheet(37/92 Pages) FREESCALE

37 / 92 page

MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

Bus Signal Timing

Table 11 shows the PCMCIA timing for the MPC885/880.

Table 11. PCMCIA Timing

Num

Characteristic

33 MHz

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

P44

A(0:31), REG valid to PCMCIA

strobe asserted 1

(MIN = 0.75

× B1 – 2.00)

1 PSST = 1. Otherwise add PSST times cycle time.

PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA

current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See

Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.

20.70

—

16.70

—

9.40

—

7.40

—

P45

A(0:31), REG valid to ALE

negation1

(MIN = 1.00

× B1 – 2.00)

28.30

—

23.00

—

13.20

—

10.50

—

P46

CLKOUT to REG valid

(MAX = 0.25

× B1 + 8.00)

7.60

15.60

6.30

14.30

3.80

11.80

3.13

11.13

P47

CLKOUT to REG invalid

(MIN = 0.25 – B1 + 1.00)

8.60

—

7.30

—

4.80

—

4.13

—

P48

CLKOUT to CE1, CE2 asserted

(MAX = 0.25

× B1 + 8.00)

7.60

15.60

6.30

14.30

3.80

11.80

3.13

11.13

P49

CLKOUT to CE1, CE2 negated

(MAX = 0.25

× B1 + 8.00)

7.60

15.60

6.30

14.30

3.80

11.80

3.13

11.13

P50

CLKOUT to PCOE, IORD,

PCWE, IOWR assert time

(MAX = 0.00

× B1 + 11.00)

—

11.00

—

11.00

—

11.00

—

11.00

P51

CLKOUT to PCOE, IORD,

PCWE, IOWR negate time

(MAX = 0.00

× B1 + 11.00)

2.00

11.00

2.00

11.00

2.00

11.00

2.00

11.00

P52

CLKOUT to ALE assert time

(MAX = 0.25

× B1 + 6.30)

7.60

13.80

6.30

12.50

3.80

10.00

3.13

9.40

P53

CLKOUT to ALE negate time

(MAX = 0.25

× B1 + 8.00)

—

15.60

—

14.30

—

11.80

—

11.13

P54

PCWE, IOWR negated to

D(0:31) invalid 1

(MIN = 0.25

× B1 – 2.00)

5.60

—

4.30

—

1.80

—

1.13

—

P55

WAITA and WAITB valid to

CLKOUT rising edge1

(MIN = 0.00

× B1 + 8.00)

8.00

—

8.00

—

8.00

—

8.00

—

P56

CLKOUT rising edge to WAITA

and WAITB invalid1

(MIN = 0.00

× B1 + 2.00)

2.00

—

2.00

—

2.00

—

2.00

—

MPC885ZP80 データシート(PDF) 37 Page - Freescale Semiconductor, Inc

MPC885ZP80 データシート(HTML) 37 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

データシートダウンロード

リンク URL

MPC885ZP80 データシート(PDF) 37 Page - Freescale Semiconductor, Inc

MPC885ZP80 データシート(HTML) 37 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

データシート ダウンロード

リンク URL

データシートダウンロード