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MPC866PCZP100A データシート(PDF) 65 Page - Freescale Semiconductor, Inc

部品番号 MPC866PCZP100A
部品情報  Hardware Specifications
PDF  96 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC866PCZP100A データシート(HTML) 65 Page - Freescale Semiconductor, Inc

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MPC866/MPC859 Hardware Specifications, Rev. 2
Freescale Semiconductor
65
CPM Electrical Characteristics
Figure 63. Ethernet Transmit Timing Diagram
Figure 64. CAM Interface Receive Start Timing Diagram
Figure 65. CAM Interface REJECT Timing Diagram
12.9 SMC Transparent AC Electrical Specifications
Table 25 shows the SMC transparent timings as shown in Figure 66.
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD1)
(Input)
133
134
132
131
121
129
RCLK1
RxD1
(Input)
RSTRT
(Output)
0
136
125
1
1
BIT1
BIT2
Start Frame Delimiter
REJECT
137



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