PLL103-02

DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

FBOUT

1

O

Feedback clock for chipset.

BUF_IN

13

I

Reference input from chipset.

PD

36

I

Power Down Control input. When low, it will tri-state all outputs.

N/C

48

Not connected.

DDR[0:11]T

4,6,10,15,19,

21,28,30,34,

39,43,45

O

These outputs provide True copies of BUF_IN.

DDR[0:11]C

5,7,11,16,20,

22,27,29,33,

38,42,44

O

These outputs provide complementary copies of BUF_IN.

VDD2.5

2,8,12,17,23,

32,37,41,47

P

2.5V power supply.

GND

3,9,14,18,26,

31,35,40,46

P

Ground.