PLL103-02

DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3

I2C BUS CONFIGURATION SETTING

Address Assignment

A6

A5

A4

A3

A2

A1

A0

R/W

1

1

0

1

0

0

1

_

Slave

Receiver/Transmitter

Provides both slave write and readback functionality

Data Transfer Rate

Standard mode at 100kbits/s

Data Protocol

This serial protocol is designed to allow both blocks write and read from the controller. The

bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred

must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will

terminate the transfer. The write or read block both begins with the master sending a slave

address and a write condition (0xD2) or a read condition (0xD3).

Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte

Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte

Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at

power-up is = (0x09).

I2C CONTROL REGISTERS

1. BYTE 6: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

48

1

Reserved

Bit 6

-

0

Reserved

Bit 5

-

0

Enhanced DDR Drive. 1 = Enhanced 25%

Bit 4

-

0

Reserved

Bit 3

45, 44

1

DDR11T, DDR11C

Bit 2

43, 42

1

DDR10T, DDR10C

Bit 1

39, 38

1

DDR9T, DDR9C

Bit 0

34, 33

1

DDR8T, DDR8C

2. BYTE 7: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

30, 29

1

DDR7T, DDR7C

Bit 6

28, 27

1

DDR6T, DDR6C

Bit 5

21, 22

1

DDR5T, DDR5C

Bit 4

19, 20

1

DDR4T, DDR4C

Bit 3

15, 16

1

DDR3T, DDR3C

Bit 2

10, 11

1

DDR2T, DDR2C

Bit 1

6, 7

1

DDR1T, DDR1C

Bit 0

4, 5

1

DDR0T, DDR0C