STPM01FTR datasheet(30/56 Pages) STMICROELECTRONICS

30 / 56 page

Theory of operation

STPM01

30/56

Each bit of parity nibble is defined as odd parity of all seven corresponding bits of data

nibbles.

The first 6 registers are read-only except for the 8 bit mode signals in the DFP register (the

mode signals will be described later in this paragraph). The last two registers CFL and CFH

can be also written because they contain the configuration bits. Among these last 64bits (32

of CFL and 32 of CFH), 8 bits are used for parity nibbles, then only 56 bits are used for

configuring and programming the STPM01.

8.19

Configuration bits

All the configuration bits that control the operation of the device (CFL and CFH data records)

can be written in a temporary or permanent way. In case of temporary writing the

configuration bits value are written in the so-called Shadow Registers which are simple

latches that hold the configuration data. In case of permanent writing the configuration bits

are stored in the OTP (one time programmable) cells that keep the information for an

undefined period of time even if the STPM01 is without supply, but, once written, they

cannot be changed anymore.

The shadow registers are cleared whenever a reset condition occurs (both POR and remote

reset).

As indicated in the data records table, the configuration bits are 56. Each of them consists of

paired elements, one is latch, the OTP shadow, and another is the OTP antifuse element.

When the STPM01 is released in the market, all antifuses represents logic low state but they

can be written by the user in order to configure the STPM01.This means that STPM01 can

Figure 22.

STPM01 Data records map

upper f(u)

mode signals

iRMS

uRMS

iMOM

uMOM

1bit

1bit 1bit

20 bit

8 bit

6 bit

11 bit

16 bit

DAP

DRP

DSP

CFH

DFP

DEV

DMV

CFL

reactive energy

type0 active energy

apparent energy

type 1 energy

lower part of configurators

upper part of configurators

Status

lower f(u)

parity

4 bit

msb

lsb

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