MF1ICS2005 datasheet(2/7 Pages) NXP

部品番号	MF1ICS2005

部品情報	Sawn bumped 120關m wafer addendum

PDF	7 Pages

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メーカー	NXP [NXP Semiconductors]

ホームページ	http://www.nxp.com

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2 / 7 page

141130

Product data sheet

Rev. 3.0 — 18 July 2007

2 of 7

NXP Semiconductors

MF1 IC S20 05

Sawn bumped 120µm wafer addendum

• Thickness:

500 nm / 600 nm

3.5 Au bump

• Bump material:

> 99.9% pure Au

• Bump hardness:

35 – 80 HV 0.005

• Bump shear strength:

> 70 MPa

• Bump height:

µm

• Bump height uniformity:

– within a die:

± 2

µm

– within a wafer:

± 3

µm

– wafer to wafer:

± 4

µm

• Bump flatness:

± 1.5

µm

• Bump size:

– LA, LB, VSS1

104 x 104

µm

– TESTIO1

89 x 104

µm

• Bump size variation:

± 5

µm

• Under bump metallization:

sputtered TiW

Remark: Substrate is connected to VSS.

3.6 Fail die identification

Electronic wafer mapping covers the electrical test results and additionally the results of

mechanical/ visual inspection.

No inkdots are applied.

1.Pads VSS and TESTIO are disconnected when wafer is sawn.

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