M65KG512AB datasheet(39/54 Pages) STMICROELECTRONICS

部品番号	M65KG512AB

部品情報	512Mbit (4 banks x 8 Mb x 16) 1.8 V supply, DDR low power SDRAM

PDF	54 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

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39 / 54 page

M65KG526AB

DC and ac parameters

39/54

Figure 17.

Write followed by Write in a different bank

If the consecutive Write operation targets an active row, the second WRIT command must be issued after a minimum delay

of tCK to interrupt the previous Write operation.

If the consecutive Write operation targets an idle row, precharge the bank (PRE) without interrupting the previous Write

operation. tRP after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD

after the ACT command.

Figure 18.

Write operation with Auto Precharge

ACT

NOP

Command

DIA0 DIA1

UDQS/

LDQS

DQ0-DQ15

DIB0 DIB1

ai11208b

Note: 1. Burst Length = 4

Row 0

Address

BA0-BA1

NOP

Row 1

DIB2

Bank A

Active

Data Read from

Bank A

Data Read from

Bank D

DIB3

WRIT

NOP

Column A Column B

Bank D

Active

tRCD

ACT

NOP

WRITEA

NOP

Command

DI0 DI1

UDQS, LDQS

DQ0-DQ15

DI2 DI3

ai10587c

Note: Burst Length = 4

tWPD

tRCD

ACT

UDQM, LDQM

tRP

tRAS(min)

Start of

Internal

Auto Precharge cycle

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