PPC405GPR-3JB266 datasheet(47/57 Pages) AMCC

47 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

Notes: 1. In all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc”

means “don’t care.”

2. See “Test Conditions” on page 42 for output capacitive loading.

I/O Specifications—Group 1 (Sheet 1 of 3)

Notes:

1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.

2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V

and I/O L is specified at 0.4 V.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(min)

I/O L

(min)

PCI Interface

PCIAD31:0

0.5

1.5

PCI Clock

PCIC3:0[BE3:0]

0.5

1.5

PCI Clock

PCIClk

async

PCIDevSel

0.5

1.5

PCI Clock

PCIFrame

0.5

1.5

PCI Clock

PCIGnt0[Req]

PCIGnt1:5

0.5

1.5

PCI Clock

PCIIDSel

PCI Clock

PCIINT[PerWE]

0.5

1.5

PCI Clock

async

PCIIRDY

0.5

1.5

PCI Clock

PCIParity

0.5

1.5

PCI Clock

PCIPErr

0.5

1.5

PCI Clock

PCIReq0[Gnt]

PCIReq1:5

PCI Clock

PCIReset

0.5

1.5

PCI Clock

PCISErr

0.5

1.5

PCI Clock

PCIStop

0.5

1.5

PCI Clock

PCITRDY

0.5

1.5

PCI Clock

Ethernet Interface

EMCMDClk

settable

10.3

7.1

2, async

EMCMDIO[PHYMDIO]

100

1 OPB clock

period + 10ns

1 OPB clock

period

10.3

7.1

EMCMDClk

EMCTxD3:0

10.3

7.1

PHYTX

EMCTxEn

10.3

7.1

PHYTX

EMCTxErr

10.3

7.1

PHYTX

PHYCol

10.3

7.1

2, async

PHYCrS

10.3

7.1

2, async

PHYRxClk

2, async

PHYRxD3:0

10.3

7.1

PHYRX

PHYRxDV

10.3

7.1

PHYRX

PHYRxErr

10.3

7.1

PHYRX

PHYTxClk

2, async

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