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http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

PINS DESCRIPTION

PIN

ACTIVE

TYPE

DESCRIPTION

clk

-

input

Global system clock

por

Low

input

Power on reset vector fetch

cmf

Low

input

Clock monitor fail vector fetch

prgdata[7:0]

-

input

Program memory bus input

ready

Low

input

Ready for Code and Data mem.

datai[7:0]

-

input

Memory bus input

ufrdatai[7:0]

-

input

UFRs data bus input

irq

*

input

Interrupt input

xirq

Low

input

Non-maskable interrupt input

portxi[7:0]

-

input

Port A, B, C, D input

cap1,2,3

Low

input

Capture inputs

pai

*

input

Pulse accumulator input

rxd

Low

input

SCI receiver data input

si

High

input

SPI slave input

mi

High

input

SPI master input

scki

*

input

SPI clock input

ss

Low

input

SPI slave select

prgaddr[15:0]

-

output

Program memory address bus

prgoe

-

output

Program memory output enable

datao[7:0]

-

output

Data memory & UFR bus output

addr[23:0]

-

output

Data memory address bus

ramwe

Low

output

Data memory write enable

ramoe

Low

output

Data memory output enable

ufraddr[7:0]

-

output

UFR address bus

ufrwe

Low

output

UFRs write enable

ufroe

Low

output

UFRs output enable

lir

Low

output

Load instruction register

halt

High

output

Halt clock system (STOP inst.)

portxo[7:0]

-

output

Port A, B, C, D output

ddrx[7:0]

-

output

Port A, B, C, D direction control

cmp1,2,3,4,5

*

output

Compare outputs

cmp1en,2,3,4,5

High

output

Output compare enable

txd

Low

output

SCI transmitter data output

so

High

output

SPI slave output

mo

High

output

SPI master output

scko

*

output

SPI clock output

scken

High

output

SPI clock output enable

soen

High

output

SPI Slave Output enable

clkdocd

-

input

DoCD

docddatai

-

input

DoCD

docddatao

-

output

DoCD

docdclk

-

output

DoCD

* Kind of activity is configurable

SYMBO L

iramaddr(9:0)

iramwe

iramoe

portao(7:0)

portdo(7:0)

portco(7:0)

portbo(7:0)

portai(7:0)

portbi(7:0)

portci(7:0)

portdi(7:0)

iramdata(7:0)

ufrdatai(7:0)

irq

xirq

pai

cap1

cap2

cap3

clk

rxd

datao(7:0)

txd

si

mi

so

mo

soen

scki

scko

scken

ss

por

cmf

halt

ddra(7:0)

ddrd(7:0)

ddrc(7:0)

ddrb(7:0)

cmp1en

cmp2en

cmp3en

cmp4en

cmp5en

cmp1

cmp2

cmp3

cmp4

cmp5

lir

iromdata(7:0)

iromaddr(12:0)

iromoe

iromwe

ready

ufraddr(7:0)

ufrwe

ufroe

clkdocd

docddatai

docddatao

docdclk

DoCD

xramaddr(23:0)

xramwe

xramoe

xramdata(7:0

moda

modb

dataen