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compare functions are included for generating

output signals or for timing software delays.

Since the input-capture and output-compare

functions may not be familiar to all users,

these concepts are explained in greater detail.

A programmable periodic interrupt circuit

called RTI is tapped off of the main 16-bit

timer counter. Software can select one of four

rates for the RTI, which is most commonly

used to pace the execution of software rou-

tines. The COP watchdog function is loosely

related to the main timer in that the clock input

free-running counter chain. The timer sub-

system involves more registers and control

bits than any other subsystem on the MCU.

Each of the three input-capture functions has

its own 16-bit time capture latch (input-capture

register) and each of the five output-compare

functions has its own 16-bit compare register.

All timer functions, including the timer overflow

and RTI, have their own interrupt controls and

separate interrupt vectors. Additional control

bits permit software to control the edge(s) that

trigger each input-capture function and the

automatic actions that result from output-

compare functions. Although hardwired logic

is included to automate many timer activities,

this timer architecture is essentially a soft-

ware-oriented system. This structure is easily

adaptable to a very wide range of applications

although it is not as efficient as dedicated

hardware for some specific timing applica-

tions.

SCI

- The SCI is a full-duplex UART type

asynchronous system, using standard non

return to zero (NRZ) format : 1 start bit, 8 or 9

data bits and a 1 stop bit. The DF6811 resyn-

chronizes the receiver bit clock on all one to

zero transitions in the bit stream. Therefore

differences in baud rate between the sending

device and the SCI are not as likely to cause

reception errors. Three logic samples are

taken near the middle of data bit time, and

majority logic decides the sense for the bit.

For the start and stop bits seven logic sam-

ples are taken. Even if noise causes one of

these samples to be incorrect, the bit will still

be received correctly. The receiver also has

the ability to enter a temporary standby mode

(called receiver wakeup) to ignore messages

intended for a different receiver. Logic auto-

matically wakes up the receiver in time to see

the first character of the next message. This

wakeup feature greatly reduces CPU over-

head in multi-drop SCI networks. The SCI

transmitter can produce queued characters of

idle (whole characters of all logic 1) and break

(whole characters of all logic 0). In addition to

the usual transmit data register empty (TDRE)

status flag, this SCI also provides a transmit

complete (TC) indication that can be used in

applications with a modem.

SPI Unit

– it’s a fully configurable mas-

ter/slave Serial Peripheral Interface, which

allows user to configure polarity and phase of

serial clock signal SCK. It allows the micro-

controller to communicate with serial periph-

eral devices. It is also capable of interproces-

sor communications in a multi-master system.

A serial clock line (SCK) synchronizes shifting

and sampling of the information on the two

independent serial data lines. SPI data are

simultaneously transmitted and received. SPI

system is flexible enough to interface directly

with numerous standard product peripherals

from several manufacturers. Data rates as

high as CLK/8. Clock control logic allows a

selection of clock polarity and a choice of two

fundamentally different clocking protocols to

accommodate most available synchronous

serial peripheral devices. When the SPI is

configured as a master, software selects one

of four different bit rates for the serial clock.

Error-detection logic is included to support

interprocessor

communications.

A

write-

collision detector indicates when an attempt is

made to write data to the serial shift register

while a transfer is in progress. A multiple-

master mode-fault detector automatically dis-

ables SPI output drivers if more than one SPI

devices simultaneously attempts to become

bus master.

Pulse Accumulator

– This system is based

on an 8-bit counter and can be configured to

operate as a simple event counter or for gated

time accumulation. Unlike the main timer, the

8-bit pulse accumulator counter can be read

or written at any time (the 16-bit counter in the

main timer cannot be written). Control bits

allow the user to configure and control the

pulse accumulator subsystem. Two maskable

interrupts are associated with the system,

each having its own controls and interrupt

vector. The PAI pin associated with the pulse

accumulator can be configured to act as a

clock (event counting mode) or as a gate sig-

nal to enable a free-running E divided by 64

clock to the 8-bit counter (gated time accu-

mulation mode). The alternate functions of the