All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

DoCD

No internal reset generator or gated clock

Scan test ready

Technology independent HDL source code

Core can be fully customized

1 GHz virtual clock frequency compared to

original implementation

Processor execution control

Read, write all processor contents

Hardware execution breakpoints

Three wire communication interface

DESIGN FEATURES

The DF6811 has 3 reset vectors

sources, which easy identify a cause of

system reset.

SYNCHRONIZED BEFORE INTERNAL USE

The DF6811 can address up to 16M

bytes of Data Memory via the function in-

terconnect signals. The 256 bytes of Data

Memory in every 64k page is reserved for

the Function Registers. Extra DPP (Data

Page Pointer) register is used for segments

swapping. Data Memory can be imple-

mented as synchronous or asynchronous

RAM.

Up to 256 System Function Regis-

ters(SFRs) may be implemented to the

DF6811

design.

SFRs

are

memory

mapped into Data Memory within any 64k

bytes address space

.

Up to 64kB of Program Memory may be

implemented to the DF6811 design. Pro-

gram Memory can be implemented as syn-

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor

and major versions changes

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Delivery the documentation updates

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Phone & email support

CONFIGURATION

The following parameters of the DF6811CPU

core can be easy adjusted to requirements of

dedicated application and technology. Con-

figuration of the core can be prepared by ef-

fortless

changing appropriate constants in

package file. There is no need to change any

parts of the code.

- used

- unused

- Harvard

- Von Neumann

- Synchronous

- Asynchronou

- 64 kB

- 16 MB

- used

- unused

- used

- unused

- used

- unused

- used

- unused