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BLOCK DIAGRAM

Control Unit

- Performs the core synchroniza-

tion and data flow control. This module man-

ages execution of all instructions. The Control

Unit also manages execution of STOP instruc-

tion and waking-up the processor from the

STOP mode.

Opcode Decoder

- Performs an instruction

opcode decoding and the control functions for

all other blocks.

ALU

- Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. It contains accumulator

(A, B), Condition Code Register (CCREG),

and related logic like arithmetic unit, logic unit,

multiplier and divider.

Bus Controller

– Program Memory, Data

Memory & SFR’s (Special Function Register)

interface controls access into the program and

data memories and special registers. It con-

tains Program Counter (PC), Stack Pointer

(SP) register, INIT register (INIT), Data Page

Pointer (DPP), Stretch register (ST) and re-

lated logic.

datao(7:0)

clk

datai(7:0)

BUS

Controller

Opcode

Decoder

Control

Unit

Interrupt

Controller

irq

por

xirq

ramoe

ramwe

addr(23:0)

halt

cmf

lir

ALU

prgdata(7:0)

prgaddr(15:0)

prgoe

ufroe

ufrwe

ready

ufraddr(7:0)

ufrdatai(7:0)

DoCD

TM

Debugger

docdclk

docddatai

docddatao

prgwe

clkdocd

Interrupt Controller

- DF6811CPU has im-

plemented only an external interrupts from

pins IRQ and XIRQ. The interrupts are acti-

vated at low level (XIRQ,IRQ pins) or falling

edge (IRQ pin) and are sampled each 1 sys-

tem clock at the rising edge of CLK.

DoCD

ware debugger provides debugging capability

of a whole SoC system. In contrast to other

on-chip debuggers DoCD™ provides non-

intrusive debugging of running application. It

can halt, run, step into or skip an instruction,

read/write any contents of microcontroller in-

cluding all registers, internal, external, pro-

gram memories, all SFRs including user de-

fined peripherals. Hardware breakpoints can

be set and controlled on program memory,

internal and external data memories, as well

as on SFRs. Hardware breakpoint is executed

if any write/read occurred at particular address

with certain data pattern or without pattern.

face and complete set of tools to communi-

cate and work with core in real time debug-

ging. It is built as scalable unit and some fea-

tures can be turned off to save silicon and

reduce power consumption. A special care on

power consumption has been taken, and

when debugger is not used it is automatically

switched in power save mode. Finally whole

debugger is turned off when debug option is

no longer used.

OPTIO N AL M O DULES

There are also available an optional pe-

ripherals,

not

included

in

presented

DF6811CPU Microcontroller Core. The op-

tional peripherals, can be implemented in mi-

crocontroller core upon customer request.

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Four 8-bit I/O Ports

Interrupt Controller

20 interrupt sources

17 priority levels

Dedicated Interrupt vector for each interrupt

source

Main16-bit timer/counter system

16 bit free running counter

Four stage programmable prescaller

Timer clocked by internal source

Real Time Interrupt

16-bit Compare/Capture Unit

Three independent input-capture functions

Five output-compare channels

Events capturing

Pulses generation

Digital signals generation

Gated timers

Sophisticated comparator