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AD9913/PCBZ1 データシート(PDF) 24 Page - Analog Devices

部品番号 AD9913/PCBZ1
部品情報  Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
PDF  32 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9913/PCBZ1 データシート(HTML) 24 Page - Analog Devices

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AD9913
Rev. 0 | Page 24 of 32
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
The user supplies PCLK, CS, R/W, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
2.
CS, R/W, and the address lines must meet the setup and
hold times relative to the 1st PCLK rising edge.
3.
The user releases the bus to read.
4.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
5.
CS must meet the set up and hold times to the 3rd PCLK
rising edge.
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
1.
The user supplies the PCLK, CS, R/W, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
2.
CS, R/W, and the address lines must meet the set up and
hold times relative to the 1st PCLK rising edge.
3.
Data lines must meet the set up and hold times relative to
the 2nd PCLK rising edge.
4.
CS must meet the set up and hold times relative to the 3rd
PCK rising edge.
PCLK
READ OPERATION
ADDR0
DATA0
DATA1
ADDR1
CS
R/W
ADDR/DATA
0.3ns
tCHD
tCSU
tDVLD
tAHD
tASU
3ns
0.3ns
8ns
3ns
Figure 33. Parallel Port Read Timing
PCLK
WRITE OPERATION
ADDR/DATA
CS
R/W
DATA1
ADDR1
DATA0
ADDR0
0.3ns
tCHD
0.3ns
tDHD
3ns
tDSU
3ns
tASU
0.3ns
tAHD
3ns
tCSU
Figure 34. Parallel Port Write Timing



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