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About the Cortex-R82 Processor

The processor has optional:

Tightly Coupled Memories (TCMs) that are private to each core, an ITCM for

instructions and literal pool data and a DTCM for data.

Shared (between all cores), and unified (instructions and data) L2 cache.

Shared AXI5 256-bit Low-latency RAM (LLRAM) port for instruction and

data access.

Shared AXI5 64-bit Shared Peripheral Port (SPP) for peripheral access.

Per-core AXI5 32-bit Low-latency Peripheral Port (LLPP) for peripheral access.

Error Correcting Code (ECC), Single Error Correct Double Error Detect (SECDED)

or Double Error Detect (DED) protection for all instantiated cache tag and data

RAMs and the TCM RAMs.

Support for integrating CoreSight Embedded Logic Analyzer, ELA-600 for advanced

debug capability and signal observability.

Block Diagram

Figure 2: Cortex-

R82 processor components