AD4052BCPZ-R2 datasheet(19/66 Pages) AD

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Data Sheet

AD4052/AD4058

THEORY OF OPERATION

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Rev. B | 19 of 66

The AD4052/AD4058 serial interface outputs the ADC data into

multiples of bytes to maximize compatibility with microcontroller

direct memory access (DMA) controllers. The ADC Mode Output

Data Format section describes the serial interface data packet

format for each of the AD4052/AD4058 operating modes.

As described in the Wide Input Common-Mode Range section,

the AD4052/AD4058 support arbitrary input common-mode voltag-

es, therefore the devices inherently support both differential and

single-ended type signals. The AD4052/AD4058 support both twos

complement (signed) and straight binary (unsigned) formats to map

either differential signals or single-ended signals to the full 16-bit

ADC transfer function. The DATA_FORMAT bit in the ADC_MODES

mode transfer functions as seen in Table 11 and Table 12.

Figure 37. ADC Ideal Transfer Function

Table 11. ADC Input Voltage to Output Code Mapping (Sample Mode)

Description

Differential Mode

Single-Ended Mode

VIN

Digital Output Code

VIN

Digital Output Code

FSR − 1 LSB

(32767/32768) × VREF

0x7FFF

(65535/65536) × VREF

0xFFFF

...

Midscale + 1 LSB

(1/32768) × VREF

0x0001

(32769/65536) × VREF

0x8001

Midscale

0 V

0x0000

(½) × VREF

0x8000

Midscale − 1 LSB

−(1/32768) × VREF

0xFFFF

(32767/65536) × VREF

0x7FFF

...

…

...

−FSR + 1 LSB

(−32767/32768) × VREF

0x8001

(1/65536) × VREF

0x0001

−FSR

−VREF

0x8000

0 V

0x0000

Table 12. ADC Input Voltage to Output Code Mapping (Averaging and Burst Averaging Modes)

Description

Differential Mode

Single-Ended Mode

VIN

Digital Output Code

VIN

Digital Output Code

FSR − 1 LSB

(524287/524288) × VREF

0x7FFFF

(1048575/1048576) × VREF

0xFFFFF

...

Midscale + 1 LSB

(1/524288) × VREF

0x00001

(524289/1048576) (8193/16384)

× VREF

0x80001

Midscale

0 V

0x00000

(½) × VREF

0x80000

Midscale − 1 LSB

(−1/524288) (−1/8192) × VREF

0xFFFFF

(524287/1048576) × VREF

0x7FFFF

...

…

...

−FSR + 1 LSB

(−524287/524288) × VREF

0x80001

(1/1048576) × VREF

0x00001

−FSR

−VREF

0x80000

0 V

0x00000

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