ADBMS6821 datasheet(21/28 Pages) AD

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Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

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Rev. B | 21 of 28

Table 22. Estimated IVDD/VP in Different Power States

State

MSTR

Estimated IVDD/VP

Idle

0 (peripheral)

10 µA

1 (controller)

10 µA

Ready

0 or 1

2.7 mA

Active

0 (peripheral)

2.7 mA + IDRV × t1/2PW(D)/tCLK

1 (controller)

2.7 mA + IDRV × 2 × t1/2PW(D)/tCLK

IDLE MODE AND WAKE-UP DETECTION

To conserve power, the ADBMS6821/ADBMS6822 transceivers in

peripheral mode (MSTR = 0) enter an idle state after tIDLE of

inactivity on the IP and IM pins. In this condition, IDD is reduced to

less than 10 µA and the SPI pins are idled (CS = 1, PICO = 1, and

SCK = POL).

The transceiver continues monitoring the IP and IM pins using a low

power, AC-coupled detector. It wakes up when it sees a differential

signal of VWAKE or greater that persists for tDWELL or longer. In

practice, a long (CS) isoSPI pulse is sufficient to wake the device

up. After the comparator generates the wake-up signal, it can take

up to tREADY for bias circuits to stabilize.

Figure 39 shows the sequence of waking up a peripheral transceiv-

er (placing it in the ready state), which uses it to communicate, then

allows it to return to the low-power idle state. For a transceiver in

controller mode (MSTR = 1), in addition to the previously mentioned

wake-up procedure, taking CS low also enables the isoSPI port

within tREADY. Then CS can be taken high, and the resulting long

pulse on the isoSPI ports serves as a wake-up signal for the periph-

eral device that is connected to this transceiver, which responds by

entering the ready state.

The controller transceiver remains in the ready or active state as

long as CS = 0. If CS transitions high, it enters the idle state after

tIDLE expires. The tIDLE time prevents the device from shutting down

between data packets.

Figure 39. Peripheral ADBMS6821/ADBMS6822 Wake-Up/Idle Timing

WAKE PIN

The WAKE pin is a current-limited output that indicates the state

of the ADBMS6821/ADBMS6822 transceivers. If a transceiver is in

the ready or active state, WAKE is logic high. If a transceiver is in

the idle state, WAKE is logic low. The WAKE pin does not indicate

interrupts for the LPCM feature. Instead, the INTR pin performs that

function.

Although the WAKE pin is normally used as an output, it can also

be used as an input when a transceiver is configured with the

MSTR pin driven logic low and the XCVRMD pin is not configured

for LPCM timeout monitor support. In this configuration, if the trans-

ceiver is in the idle state and outputting a logic low on the WAKE

pin, externally driving the WAKE pin high for at least tREADY causes

the transceiver to transition from the idle state to the ready state

and then transmit a wake-up pulse on the isoSPI port. This wake-up

pulse can be used, for example, by a peripheral transceiver to wake

up the controller transceiver without changing the direction of the

isoSPI bus from peripheral to controller.

Consider the following example. The controller and peripheral

transceivers are in a low-power state. The peripheral controller

requires attention from the controller. The peripheral drives the

WAKE pin of the peripheral transceiver high, which wakes up the

peripheral transceiver and causes a wake-up pulse to be transmit-

ted to the controller transceiver. The controller transceiver then

wakes up and drives its WAKE pin logic high, which alerts the

attached controller that the peripheral needs attention.

When the WAKE pin is used as an input, the signal that drives

the WAKE pin can range from WAKE pin VIH to 6 V (WAKE pin

absolute maximum) to allow the transceiver to detect a logic high.

The WAKE pin is powered from the VP or VDD pin. Therefore, the

WAKE pin does not need the VDDS pin to be supplied to operate.

The WAKE output is current-limited to IPU(WAKE/INTR) for pull-up

and to IPD(WAKE/INTR) for pull-down. The maximum output voltage

of the WAKE pin is specified by VPU(WAKE/INTR). If that voltage is

not compatible with the input voltage limit of a connected device, a

Zener diode clamp or a level shifter may be required.

MULTIDROP

Multiple peripherals can be connected to a single controller by con-

necting them in parallel (multidrop configuration) along one cable.

As shown in Figure 40, terminate the cable only at the beginning

(controller) and the end. In between, the additional ADBMS6821/

ADBMS6822 devices and their associated peripheral devices are

connected to stubs on the cable. Keep these stubs short, with as

little capacitance as possible, to avoid degrading the termination

along the cable. The multidrop configuration is only possible if the

SPI peripherals have the following characteristics:

►

The SPI peripherals must be addressable, because they all see

the same CS signal (as decoded by each peripheral transceiver).

►

When not addressed, the peripheral SDO must remain high.

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