ADBMS6821 datasheet(23/28 Pages) AD

23 / 28 page

Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

analog.com

Rev. B | 23 of 28

LPCM TIMEOUT MONITOR

The ADBMS6821/ADBMS6822 transceivers can be configured to

work as the timeout monitor in systems using the LPCM feature

of select ADBMS battery monitors. During LPCM operation, the bat-

tery monitors can be configured to monitor the cell stack for a varie-

ty of alert conditions and regularly communicate this condition by

sending heartbeat messages to the transceiver, all while consuming

very low average power. The transceiver monitors these heartbeat

messages from the battery monitors to determine whether to assert

the INTR pin high to alert the microcontroller. A simplified block

diagram of an LPCM BMS system is shown in Figure 41.

Figure 41. Simplified LPCM BMS

To function as a timeout monitor, the XCVRMD pin must have a 20

kΩ pull-down to GND, and the RTO pin condition sets the timeout

period for the timeout monitor. The microcontroller drives the MSTR

pin high while communicating through the transceiver to the BMS

devices. To enable the LPCM operation, the microcontroller first

configures the ADBMS battery monitors for LPCM operation and

then drives the MSTR pin low to activate the timeout monitor

feature of the transceiver.

When the timeout monitor is activated by driving MSTR pin low, the

transceiver initially asserts the INTR pin high. The timeout monitor

assumes that until the first heartbeat message has fully propagated

through the daisy chain, there may be a fault in the system in the

initial state. This transition of the INTR pin from low to high also

serves as an indication to the microcontroller that the timeout mon-

itor function has been activated. The INTR pin remains asserted

high until a pass heartbeat message is received from the battery

monitors. The battery monitors are designed to initiate the first

heartbeat sequence quickly after initially enabling LPCM operation.

Thus, the initial status of the cell stack is quickly evaluated and

the INTR pin is deasserted low if no faults are indicated. Leaving

the INTR pin asserted until the cell stack is evaluated provides the

microcontroller with further confirmation that the LPCM operation

has begun and the cell stack is not in an unexpected condition.

After the INTR pin is deasserted low, the internal timer is reset to 0.

If a pass heartbeat message is received before the timeout period,

INTR remains low and the internal timer is reset again, which starts

another timeout period. If a fail heartbeat message is received or

if the timeout expires, INTR is asserted high. The INTR pin gives

an alert when a failure is indicated by the battery monitors or cases

where the communication link has failed. INTR can connect to an

interrupt pin on the microcontroller to wake it up, or it can be used

to turn on a power supply to power up the BMS controller.

After timeout monitor operation has begun, the VDD and VDDS

pins are not required to be supplied. The system can choose to

disable power to these supplies to limit power consumption in the

system. The INTR pin output can operate from the power supplied

to the VP pin. The isoSPI output drivers on the IP pin and IM pin

are not active. Therefore, the VDD pin supply is not required.

If the VDDS pin is supplied during timeout monitor operation, the

transceiver continues to translate any received isoSPI traffic to the

SPI port, which allows the microcontroller to observe the heartbeat

messages and confirm that LPCM is working properly. The micro-

controller can also diagnose the ability of LPCM to detect failure

by forcing a failure detection in the configuration of the battery

monitors and confirming that the INTR pin indicates the failure.

To exit timeout monitor operation, supply the VDD and VDDS pins,

drive the MSTR pin high (the INTR pin deasserts low), and then

send a communication sequence to the battery monitors to end

their LPCM operation. The microcontroller can then resume normal

communication with the battery monitors.

LPCM RTO (RESISTOR TIMEOUT) PIN

The RTO pins on the ADBMS6821/ADBMS6822 transceivers set

the timeout period when the device is configured as an LPCM time-

out monitor. The timeout period settings are defined to be 50% larg-

er than the corresponding measurement period used on the LPCM

battery monitors to allow variance in the oscillator performance

between the battery devices and the transceiver. The suggested

1% resistor values for the timeout periods and the corresponding

LPCM measurement periods are shown in Table 23.

Table 23. RTO Resistor Selection

Timeout Period (sec)

RTO Resistor (kΩ) to GND

Measurement

Period (sec)

1.5

GND or 100

17.8

30.9

43.2

56.2

68.1

80.6

LPCM INTR PIN

The INTR pins of the ADBMS6821/ADBMS6822 transceivers are

current-limited outputs that indicate the LPCM interrupt state when

the device is configured as a timeout monitor. For the description of

the INTR operation, see the LPCM Timeout Monitor section.

The INTR output is current-limited to a nominal 20 µA (both for

pull-up and pull-down). The maximum output voltage can range

from VDD − 1.5 V to VDD (no DC loadings) depending on the supply

voltage of the VP and VDD pins. If that voltage is not compatible

with the input voltage limit of a connected device, a Zener diode

clamp or a level shifter may be required.

ADBMS6821 データシート(PDF) 23 Page - Analog Devices

ADBMS6821 データシート(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

データシートダウンロード