ADL6337ACRZA-R7 datasheet(6/53 Pages) AD

部品番号	ADL6337ACRZA-R7

部品情報	35 dB Gain, 500 MHz to 5200 MHz Transmit VGA

PDF	53 Pages

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メーカー	AD [Analog Devices]

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6 / 53 page

Data Sheet

ADL6337

SPECIFICATIONS

analog.com

Rev. E | 6 of 53

Table 3. SPI AC Timing (Continued)

Parameter

Description

Min

Typ

Max

Unit

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tDCS

Setup time between falling edge of CS and rising edge of SCLK

Hold time between rising edge of CS and the last falling edge of SCLK, minimum 10 ns

tDV

Maximum time delay between falling edge of SCLK and output data valid for a read operation

Maximum time delay between CS deactivation and SDIO bus return to high impedance

Timing Diagrams

Figure 2. SPI Register Timing, MSB First

Figure 3. Timing Diagram for the SPI Register Write (3- and 4-Wire SPI Mode)

Figure 4. Timing Diagram for SPI Register Read (4-Wire SPI Mode)

Figure 5. Timing Diagram for SPI Register Read (3-Wire SPI Mode, SDIO Pin is Bidirectional Mode)

ADL6337ACRZA-R7 データシート(PDF) 6 Page - Analog Devices