TDA7546 datasheet(27/68 Pages) STMICROELECTRONICS

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TDA7546

Functional description

27/68

5.2

RDS decoder

5.2.1

Overview

The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip.

It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio

broadcasting stations.

The oscillator frequency is 10.25MHz and is derived from the tuner. The fractional PLL must

be initialized through I2C/SPI interface to generate the internal 8.55 MHz or 8.664 MHz

reference clock (toll).

Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all

further processing is done in the digital. After filtering the highly over sampled output of the

A/D converter, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal

and the quality information. A next RDS/RBDS decoder will synchronize the bit wise RDS

stream to a group and block wise information. This processing includes an error detection

and error correction algorithm. In addition, an automatic flywheel control avoids overheads

in the data exchange between the RDS/RBDS processor and the host.

The device operates in accordance with the CENELEC Radio Data System (RDS)

specification EN50067.

5.2.2

Fractional PLL

Figure 4.

Fractional PLL

The fractional PLL (Figure 4) is used to generate from the XTI input clock one of the two

possible system clocks (fsys) 8.55 MHz or 8.664 MHz. For this a setting for the input diver

Phase

Comperator

& VCO

Input

Divider

Output

Divider

Fractional

Divider

PLL Controller

Mux

f(vco)

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