AFE0064

SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com

A high pulse on STI activates the data read function and resets the channel counter to zero. As shown in

Figure 5, the device outputs the analog voltage from channel 63 on the first rising edge of CLK after STI falling

edge. Channel 63 to 32 data is available on the OUTP<1> and OUTM<1> terminals. Next the lower output

channel is connected to the output after four clocks.

Data on the OUTP<0> and OUTM<0> terminals is skewed by two clocks with respect to OUTP<1> and

OUTM<1>. Channel 31 to 0 data is available on the OUTP<0> and OUTM<0> terminals.

The skew between the two output drivers allows the user to connect a two channel multiplexed input ADC to the

AFE output.

The device output goes to 3-state after all of the data on the particular differential output driver ( 0 or 1) is

transferred, if ENTRI is tied to high level. Otherwise, both differential output drivers stay at output common-mode

voltage after data transfer.

Maximum Data Transfer Rate: As shown in Figure 5, the device outputs new channel data on every alternate

rising edge of the clock. Effectively the data transfer rate is one-half of the clock speed. The maximum data

transfer rate is 7.5 MHz as the device supports a maximum 15 MHz clock frequency.

Figure 6. Device Data Read in Simultaneous Mode ( SMT_MD=1)

A high level on the ‘SIMULT_MODE’ pin selects simultaneous mode. the device outputs data simultaneously on

both differential output drivers OUTP-OUTM<0> and OUTP-OUTM<1> in this mode. This means the device

outputs both Ch31 and Ch63 outputs on the first rising edge of the clock, Ch30 and Ch62 on the 2nd rising edge

and so on. This mode is useful when two separate single channel ADCs or one simultaneous sampling ADC is

used to digitize OUTP-OUTM<0> and OUTP-OUTM<1>. Unlike sequential mode, simultaneous mode needs only

33 clocks to read all 64 channels of data. In this case the output data transfer rate per output driver is the same

as the clock frequency. The device can work at a maximum clock frequency of 3.75 MHz.

Running the Device at Minimum Scan Time:

Minimum scan time is achieved if a data read overlaps the reset phase (as shown in Figure 1). This can be done

if an IRST rising edge and STI rising edge occur simultaneously. It is recommended to stop the clock after the

device receives 133 clocks after STI falling edge, if sequential mode selected (or 33 clocks if simultaneous mode

is selected). It is possible to keep the clock free running throughout the scan, but it can potentially deteriorate

noise performance. With t-scan (min) = t1+t2+132 (t-clk)+t3+t4+t5+0.5µSec+t6+t7 and all timing values used are

the minimum specified values, then t-scan (min) = 28.32 µSec.

Running the Device at Higher Scan Time (for lesser frame rate):

It is possible to run the device at a higher scan time to achieve a lesser frame rate without affecting performance.

(Note that violating the maximum limits on the specified timings and also the minimum specification on the clock

frequency results in charge leakage on the integration or CDS capacitors. This causes additional offset and gain

errors.)

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